THERMAL COUPLING METHOD FOR REFLOW SOLDERING PROCESS
LAU CHUN SEAN
UNIVERSITI SAINS MALAYSIA
2013
THERMAL COUPLING METHOD FOR REFLOW SOLDERING PROCESS
by
LAU CHUN SEAN
Thesis submitted in fulfillment of the requirements for the degree of
Doctor of Philosophy
July 2013
II
DECLARATION
I hereby declare that the work reported in this thesis is the result of my own investigation and that no part of the thesis has been plagiarized from external sources.
Materials taken from other sources are duly acknowledged by giving explicit references.
Signature: ………..
Name of student: LAU CHUN SEAN Matrix number: P-CD 0091
Date: 25 March 2013
III
ACKNOWLEDGEMENTS
First and foremost, I would like to express my gratitude to my supervisor, Professor Mohd Zulkifly Abdullah for his extremely supportive and ever accessible throughout this research work. His expertise, understanding, and patience, added considerably to my graduate experience and without his encouragement and personal guidance, it would have been provided a good basis for the present thesis.
I gratefully acknowledge the financial support of the Ministry of Higher Education of Malaysia for the FRGS grant scheme. Moreover, I would like to thank Professor Delfim Fernandes Soares and Professor José Carlos Fernandes Teixeira for allowing me accesses to the facilities in Universidade do Minho (UM), Portugal for my experimental and working conditions involved in this study. In particular, the helpful discussion and technical support extended by Professor Delfim Fernandes Soares is highly appreciated. Special thanks to Celestica (M) Sdn. Bhd., Intel Technology (Kulim), Qualitek Singapore (PTE.) Ltd and Fintexs Technologies Sdn. Bhd. for their sharing information and knowledge.
I also thank all the staff of the Institute of Postgraduate Studies, Universiti Sains Malaysia (USM) for their countless efforts and support in organize the PPD Workshops, which provided useful ideas in my research work. Besides, I extend my warmest thanks to all staff and technicians in School of Mechanical Engineering, USM who have helped me during the research.
I am honored to have chance to work with many excellent researchers during my tenure in thermo-fluid group, USM and functionalized materials and surfaces
IV
performance group, UM. Special thanks to all my colleagues for whom I have great regard, especially Khor, Leong, Ong, Dandan and Sonia.
Last but not the least, I would like to thank to my parents, my sisters, my girlfriend, my friends and whom I love with all my heart, for their support, tolerance and encouragement, which have enabled me to complete this project. They have given me inspiration to work hard and motivated me during this research work.
Lau Chun Sean February 2013
V
TABLE OF CONTENTS
ACKNOWLEDGEMENTS ...III TABLE OF CONTENTS ...V LIST OF TABLES ... XI LIST OF FIGURES...XIV LIST OF SYMBOLS ...XXI LIST OF ABBREVIATIONS ...XXIV ABSTRAK ... XXVII ABSTRACT ...XXIX
CHAPTER 1 - INTRODUCTION
1.1 Surface mount technology...1
1.2 Surface mount assembly and challenges ...5
1.3 Problem statement ...6
1.4 Objectives of the study ...9
1.5 Scope of the research work ...10
1.6 Contribution of study ...10
1.7 Thesis outline ...12
CHAPTER 2 - LITERATURE REVIEW 2.1 Introduction ...13
2.2 Ball Grid Array (BGA) technology...13
2.3 Reflow soldering process ...18
2.3.1 The reflow oven ...21
VI
2.3.2 Reflow thermal profiling ...24
2.4 Modeling the reflow soldering process ...27
2.4.1 Board- level analysis...27
2.4.2 Package- level analysis ...32
2.5 Solder joint reliability...35
2.5.1 Reliability test of solder joint under ATC ...37
2.5.2 Defect mechanism analysis during reflow soldering process ...39
2.6 Optimization method...43
2.6.1 Optimization of reflow soldering process...43
2.6.2 Application of design of experiment (DOE) ...46
2.6.3 Approach for solving the multiple quality characteristics of DOE ...47
2.7 Summary ...48
CHAPTER 3 - METHODOLOGY 3.1 Introduction ...51
3.2 Experimental details for thermal profiling ...53
3.2.1 Forced-convection reflow oven ...53
3.2.2 Forced convection-IR reflow oven ...58
3.3 Description of numerical method ...61
3.3.1 Governing equations of the reflow oven ...62
3.3.2 Boundary conditions of reflow oven ...64
3.3.3 Finite volume method (FVM)...64
3.3.4 Governing equations of the BGA assembly ...65
3.3.5 Boundary conditions of BGA assembly ...66
VII
3.3.6 Finite element method (FEM) ...68
3.4 Numerical model and implementation in reflow soldering process ...69
3.4.1 Board- level analysis...69
3.4.1.1 Board- level CFD model ...69
3.4.1.2 Board- level structural model ...71
3.4.1.3 Coupling of board- level CFD and structural models ...73
3.4.1.4 Complexity of the board- level BGA assembly ...74
3.4.1.5 Variations of conveyor speed ...75
3.4.2 Package- level analysis ...75
3.4.2.1 Geometry ...76
3.4.2.2 Package- level CFD model...77
3.4.2.3 Package- level structural model ...79
3.4.2.4 Coupling of package- level CFD and structural models ...81
3.4.2.5 Variations of solder joint arrangement pattern...81
3.4.3 Failure location verification under ATC ...83
3.4.3.1 Package materials and properties ...83
3.4.3.2 FEA modeling method ...84
3.4.3.3 Thermo-cyclic loading ...85
3.4.3.4 Fatigue life prediction method ...86
3.5 Optimization procedures ...87
3.5.1 Analysis of S/N ratio, simple analysis and ANOVA...89
3.5.2 Grey relational analysis with entropy weighting ...92
3.5.3 Case study 1: Optimization of cooling stage of lead- free reflow process ...94
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3.5.4 Case study 2: Optimization of the lead- free reflow soldering process ...97
3.5.4.1 Numerical model ...97
3.5.4.2 Factor and noise levels ...99
3.5.4.3 Experimental setup for confirmation test ...102
CHAPTER 4 - RESULTS AND DISCUSSIONS 4.1Introduction ...109
4.2Board- level analysis ...109
4.2.1 Board- level grid independence test ...110
4.2.2 Board- level experimental validation...112
4.2.3Flow characteristic of a heating zone in convection reflow oven...116
4.2.4Flow characteristic of a cooling zone in convection reflow oven ...124
4.2.5Effect of complexity on the board- level BGA assembly ...127
4.2.6 Effect of conveyor speed on ΔT of the board-level BGA assembly ...132
4.3Package-level analysis...135
4.3.1 Package- level grid independence test ...135
4.3.2 Package- level experimental validation ...137
4.3.2.1 Lead-based soldering...138
4.3.2.2 Lead- free soldering ...139
4.3.3 Comparison of board- and package- level BGA assembly...142
4.3.4 Convective heat transfer coefficient within BGA assembly...144
4.3.5 Comparison of solder joint temperature and surface temperature ...148
4.3.6 Temperature distribution within lead-based solder joint array ...150
4.3.7 Thermal stress distribution within lead-based solder joint array ...153
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4.3.8Verification of failure location under ATC ...158
4.4 Effect of lead- free solder joint during reflow soldering process...162
4.4.1 Effect of lead- free solder joint during cooling stage of reflow process ...162
4.4.2 Effect of lead- free solder joint arrangements on temperature distribution ..164
4.4.3 Effect of lead- free solder joint arrangements on stress distribution ...168
4.5Case study 1: Optimization the cooling stage of lead-free CSP...171
4.5.1 Simulated experiment results...172
4.5.1.1 Simple analysis...172
4.5.1.2 ANOVA ...174
4.5.2Optimization for multiple performance characteristics ...177
4.5.3Confirmation test ...180
4.6Case study 2: Optimization the lead- free reflow soldering process ...182
4.6.1Numerical analysis for initial condition...182
4.6.2Response table of a single quality characteristic ...185
4.6.3Multiple quality characteristic optimization ...188
4.6.3.1 Simple analysis...188
4.6.3.2 ANOVA ...190
4.6.4Confirmation test ...191
4.6.5Experimental comparison with initial process parameter settings ...194
4.7Summary ...204
CHAPTER 5 - CONCLUSIONS 5.1 Conclusions ...205 5.2 Recommendations for future works ...205210
X
REFERENCES ...212
APPENDICES Appendix A: The specification of reflow oven and equipments...224
Appendix B: The UDF applied in simulation model ...227
Appendix C: Simulation results ...233
Appendix D: Sample calculation in optimization of reflow soldering process ...234 PUBLICATION LIST
XI
LIST OF TABLES
Page Table 2.1 Classification reflow profile for SnPb and lead-free assembly 26 Table 2.2 Desired profile features to minimize the solder joint defect (Lee,
1999)
41 Table 3.1 Temperature setting in forced convection reflow oven 57
Table 3.2 Reflow oven setting parameters 60
Table 3.3 Thermal properties used in the BGA assembly 71
Table 3.4 Dimensions of the fleXBGAT M assembly (Chen and Chen, 2006) 77 Table 3.5 Material properties used in the BGA assembly 80 Table 3.6 Creep law constants of lead-based solder (Hannach et al., 2009) 84 Table 3.7 Crack growth correction constants (Darveaux, 2000) 87
Table 3.8 Dimensions of the CSP assembly 94
Table 3.9 Reflow oven parameters and their level 96
Table 3.10 Taguchi L9 orthogonal array 96
Table 3.11 Dimensions of the BGA assembly 97
Table 3.12 Reflow oven setting parameters and their level 100
Table 3.13 Taguchi L18 orthogonal array 101
Table 4.1 Summary of grid independence test for board-level fluid meshes 110 Table 4.2 Summary of grid independence test for board-level solid meshes 111 Table 4.3 Comparison between temperature profile parameters 114 Table 4.4 The summary of the important parameters used in calculation 115 Table 4.5 Summary of grid independence test for package- level fluid
meshes
136
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Table 4.6 Summary of grid independence test for package-level solid meshes
137 Table 4.7 Comparison between temperature profile parameters 139
Table 4.8 Fatigue life prediction results 161
Table 4.9 Simulated experiment results and calculated S/N ratios 172 Table 4.10 Response table of S/N ratios for thermal stress 173 Table 4.11 Response table of S/N ratios for the cooling rate 174 Table 4.12 Results of the ANOVA with thermal stress as response 175
Table 4.13 Pooled ANOVA 175
Table 4.14 Results of the ANOVA with cooling rate as response 176
Table 4.15 Pooled ANOVA 176
Table 4.16 Gray relational coefficients of responses and gray relational grade
178 Table 4.17 Response table for overall gray relational grade 179
Table 4.18 ANOVA results with multiple responses 180
Table 4.19 The comparison results of the initial and optimal parameter settings
181
Table 4.20 Simulated experiment results 186
Table 4.21 Response table of S/N ratios for the ∆T of package-level 186 Table 4.22 Response table of S/N ratios for the ∆T of board-level 187 Table 4.23 Response table of S/N ratios for the critical thermal stress 187 Table 4.24 Response table of S/N ratios for the minimum peak temperature 188 Table 4.25 Response table of S/N ratios for the minimum reflow time 188 Table 4.26 Grey relational coefficients of responses and grey relational
grade
189
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Table 4.27 Response table for the multiple responses 190
Table 4.28 ANOVA results with multiple responses 191
Table 4.29 Pooled ANOVA 191
Table 4.30 The comparison results of the initial and optimal parameter settings
192
Table 4.31 EDS analysis results of chemical composition (in at.%) for initial condition
199 Table 4.32 EDS analysis results of chemical composition (in at.%) for
optimal condition
200
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LIST OF FIGURES
Page Figure 1.1 Types of PCB assembly technology (a) SMT (b) THT (Lee,
2002)
2 Figure 1.2 Package lead configurations (a) Gullwing (b) Butt- lead (c) J- lead
(d) Leadless metallization (e) Ball- lead (Lee, 2002)
3 Figure 1.3 Schematic diagram of Plastic BGA (Mawer, 1996) 4 Figure 1.4 Schematic of the wave-soldering process (Tarr, 1999) 5
Figure 2.1 Roadmap of BGA Technology (Toshiba, 2012) 14
Figure 2.2 The BGA Families (a) Plastic BGA (b) Ceramic BGA (c) Tape BGA (Eric, 1997; Mawer, 1996)
15
Figure 2.3 PBGA assembly process (Eric, 1997) 16
Figure 2.4 Filled array and partially filled BGA packages (Eric, 1997) 17
Figure 2.5 Amkor CSP Devices (Eric, 1997) 18
Figure 2.6 Cross-section of CSP (Lau, 1997) 18
Figure 2.7 Reflow Soldering Process 19
Figure 2.8 Stencil printing process 20
Figure 2.9 Schematic diagram of (a) Infrared reflow oven, (b) Forced convection-IR reflow oven (Son and Shin, 2005)
22 Figure 2.10 Schematic diagram of (a) forced convection reflow oven, (b)
heated plenum (Tavarez and Gonzalez, 2003)
23 Figure 2.11 Typical reflow thermal profile (Tsai, 2009) 25 Figure 2.12 Classification reflow profile (J-STD-020D1, 2008) 26 Figure 2.13 The summary of CFD model and example temperature response 30 Figure 2.14 Grid array device size for pad limited full arrays (Eric, 1997) 33 Figure 2.15 Cause and effect diagram of solder joint reliability 37
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Figure 3.1 Flowchart of proposed methodology 52
Figure 3.2 Schematic diagram of the SMT forced convection reflow oven 54 Figure 3.3 Parts of the SMT reflow oven: (a) Dual conveyor lines, (b) Part
of dimension of plenum
54
Figure 3.4 Heated zone plenum 55
Figure 3.5 (a) Cooling zone plenum (b) Remote sliding heat exchangers 55 Figure 3.6 Cross-section view of the cooling zone plenum 56 Figure 3.7 Example of a board- level PCB assembly with thermal profiler 57 Figure 3.8 Example of the thermocouple attachment on the bottom of PCB 58
Figure 3.9 Experiment setup for thermal profiling 59
Figure 3.10 Comparison the temperature setting of various type of reflow oven
60 Figure 3.11 Location of the thermocouple attachment on the PCB 61
Figure 3.12 Free body diagram 67
Figure 3.13 3-D half geometry of the reflow oven without the board- level BGA assembly
70 Figure 3.14 Computational meshes in the board- level BGA assembly 72
Figure 3.15 MpCCI coupling method 74
Figure 3.16 Various complexities of a board- level BGA assembly 75 Figure 3.17 Cross section view of the package level (b) The 3-D quarter of a
BGA assembly
76 Figure 3.18 (a) 3-D quarter geometry of the reflow oven without BGA
assembly (b) Meshed with tetrahedral grid (c) Meshing between the gap of solder joints
78
Figure 3.19 3-D quarter meshes in the package- level assembly 81 Figure 3.20 Various cases of solder joint arrangement patterns 82
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Figure 3.21 (a) 3-D global model (quarter of the whole package) (b) 3-D local model
85
Figure 3.22 Temperature cycle profile 85
Figure 3.23 Flowchart of optimization procedure 88
Figure 3.24 Board- and package- level analyses 95
Figure 3.25 (a) 3-D quarter geometry of the reflow oven without the BGA assembly. (b) Meshed with tetrahedral grid
98 Figure 3.26 (a) Cross-section view of the BGA assembly (b) 3-D quarter
meshes in the structural model of BGA assembly
99
Figure 3.27 Main experimental equipments 102
Figure 3.28 Other equipments of experiment 103
Figure 3.29 (a) Affix the stencil on the PCB without scotch tape (b) with scotch tape
103
Figure 3.30 Apply the solder paste 104
Figure 3.31 (a) Drag the mini-squeegee from right end (b) to the left end 104 Figure 3.32 (a) Initial condition before remove the stencil (b) Remove the
stencil using tweezers
105
Figure 3.33 The solder paste deposited on BGA pads 105
Figure 3.34 (a) During BGA package placement (b) After BGA package placement
106
Figure 3.35 (a) Overview of reflow oven with BGA assembly (b) Location of BGA assembly
107
Figure 3.36 Reflowing the BGA assembly in reflow oven 107
Figure 3.37 Sample preparation (a) Wait until the resin dried off (b) After dried off
108 Figure 4.1 Percentage deviation versus various mesh sizes of fluid meshes 111 Figure 4.2 Percentage deviation versus various mesh sizes of solid meshes 112
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Figure 4.3 Experimental lead-based reflow thermal profile 113 Figure 4.4 Comparison of the simulation profile against the experimental
and analytical models of lead-based soldering at Location A
113 Figure 4.5 Schematic diagram of gas flow with multiple impingement jets
(a) nozzles in a staggered configuration (b) Impinging jet flow (Inoue and Koyanagawa, 2005)
115
Figure 4.6 Simulation of the flow field in Zone 1 116
Figure 4.7 Complex flow pattern within an array of impinging jets (adapted from Weigand and Spring, 2011)
118 Figure 4.8 Velocity vector around the TPB at 24 s (a) X-axis, (b) Z-axis 119 Figure 4.9 Temperature contours in Zone 1 at various flow time 120 Figure 4.10 h values and temperature contours at the top surface of the TPB
at various flow times (H/D =9.5)
122 Figure 4.11 h values and temperature contours at the bottom surface of the
TPB at flow time of 24 s (H/D =5)
123 Figure 4.12 Simulation of the flow field and temperature contour of board-
level BGA assembly in Cooling Zone
125 Figure 4.13 Temperature contours in cooling zone of various flow times 126 Figure 4.14 Temperature distribution of the TPB at various cases, (a) Case 1,
(b) Case 2, (c) Case 3, (d) Case 4, and (e) Case 5
128 Figure 4.15 Velocity vector around the TPB at 22 s (CR=2.78) 129 Figure 4.16 Velocity vector around the TPB at 24 s for (a) CR = 2.78, (b) CR
= 6.33, and (c) CR = 22.33
130 Figure 4.17 Comparison of ΔTs in the TPB for various cases 131 Figure 4.18 Temperature profile of different location for various cases 132 Figure 4.19 Effect of variations in conveyor speeds, (a) 1.25, (b) 1.00, and
(c) 0.80 cm/s
133 Figure 4.20 Comparison of ΔT on the TPB for different conveyor speeds 134
XVIII
Figure 4.21 Temperature profile at Location A for different conveyor speeds 134 Figure 4.22 Percentage deviation versus various mesh sizes of fluid meshes 136 Figure 4.23 Percentage deviation versus various mesh sizes of solid meshes 137 Figure 4.24 Simulation and experimental temperature profile for lead-based
soldering
138
Figure 4.25 Experimental lead- free reflow thermal profile 140 Figure 4.26 Comparison of the simulation with the experimental profile of
the cooling stage for lead-free soldering
140 Figure 4.27 Simulation and experimental thermal reflow profile for lead-free
soldering
142 Figure 4.28 Temperature distribution for the board and package level model 143 Figure 4.29 Temperature profile for the board and package level model of the
cooling stage at center point of package
143 Figure 4.30 Convective heat transfer coefficient contour of quarter BGA
assembly
145 Figure 4.31 Average heat transfer coefficient of different BGA assembly
surfaces
146 Figure 4.32 Temperature values along the fluid velocity vectors within the
solder gap at 230 s (a) Overview, (b) Around the solder joints
147 Figure 4.33 Comparison of solder joint temperature and surface temperature 149 Figure 4.34 The ΔT of the package-level versus time for lead-based soldering 149 Figure 4.35 Temperature distribution contour of the quarter BGA solder joint
for Zone 1, 9 and cooling zone
152 Figure 4.36 Temperature distribution for peak temperature of perimeter array
BGA solder joint
153 Figure 4.37 Displacement contour on BGA assembly for cooling zone 154 Figure 4.38 von-Mises stress contour on solder joint array at 30.64 s of
cooling time
155
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Figure 4.39 Comparison of experiment result with the simulation result 155
Figure 4.40 Predicted Curvature (Pharr, 2008) 156
Figure 4.41 Simulated Curvature 157
Figure 4.42 Thermal stress contour by contraction on the simple structure 157 Figure 4.43 Distribution of the accumulated creep strain in the global (a) and
local (b) model of lead-based solder joint
159 Figure 4.44 Comparison of experiment result with the simulation result 159 Figure 4.45 Accumulated volume-weighted average creep energy density
versus time
160 Figure 4.46 Locations of critically affected solder joints on lead-based
soldering
161 Figure 4.47 Comparison of temperature profile for lead-based and lead-free
solder
163 Figure 4.48 Temperature distribution contour of the lead- free solder array for
various joint arrangements at 60 s of cooling time
165 Figure 4.49 Comparison of ∆Ts in the solder array for various cases 166 Figure 4.50 Comparison of solder joint temperature at maximum von-Mises
stress location for various cases
167 Figure 4.51 von-Mises stress contour on solder joint array for various cases 169 Figure 4.52 Comparison of maximum fracture time at various cases 170 Figure 4.53 The response graph for each level of the reflow oven parameters
(Thermal Stress) 173
Figure 4.54 The response graph for each level of the reflow oven parameters (Cooling Rate)
174 Figure 4.55 Response graph for each level of the reflow oven parameters
(multi-responses)
179 Figure 4.56 Comparison of the von-Mises stress between the initial and
optimal conditions
182
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Figure 4.57 The ΔT of the package- and board-levels versus time 183 Figure 4.58 Reflow thermal profile of the coldest solder joint versus time 185 Figure 4.59 Comparison the initial and optimal reflow profiles of the coldest
solder joint
193 Figure 4.60 Comparison of the von-Mises stress contours between the initial
and optimal conditions
194 Figure 4.61 X-ray detection for initial and optimal conditions 195 Figure 4.62 High magnification defect Image for initial condition (a)
Spattering (b) Bridging (c) Voiding and spattering (d) Missing balls
195
Figure 4.63 Cross-section view of the BGA assembly at the (a) initial condition and (b) optimal condition
196
Figure 4.64 SEM of the BGA solder joint (left) 197
Figure 4.65 SEM of the BGA solder joint (right) 197
Figure 4.66 Area of interest for EDS analysis on initial condition (a) Z1-Z4 (b) Z5- Z9 (c) Z10
198 Figure 4.67 Area of interest for EDS analysis on optimal condition (a) Z1-Z4
(b) Z5- Z8 (c) Z9 (d) Z10 (e) Z11-12
200 Figure 4.68 Interfacial microstructures of initial and optimal conditions 201 Figure 4.69 EDS spectrum of the IMC formed in initial condition 201 Figure 4.70 EDS spectrum of the IMC formed in optimal condition 202 Figure 4.71 EDS spectrum of the Ag3Sn formed in initial condition 203 Figure 4.72 EDS spectrum of the Ag3Sn formed in optimal condition 204
XXI
LIST OF SYMBOLS
SYMBOL DESCRIPTION UNIT
Englis h Symbols
a Absorption coefficient -
A Power Law multiplier s-1
A Area of top surface of PCB m2
Surface area for heat transfer by convection m2
B Hyperbolic law multiplier MPa-1
cp Specific heat capacity of structure J/Kg.K
Cp Specific heat at constant pressure for the fluid J/Kg.K Cv Specific heat at constant volume for the fluid J/Kg.K
D Diameter of the orifices cm
E Young Modulus MPa
F Force N
FA F-ratio -
f Heat flux W/m2
H Distances between orifice and the assembled PCB cm
Activation energy J/mol
havg Average convective heat transfer coefficient W/m2.K
I Radiation intensity -
h Convection heat transfer coefficient W/m2.K
k Thermal conductivity of the gas W/m.K
K-ε Turbulent kinetic energy (K) and the turbulent dissipation rate (ε)
-
n Stress order -
P Total area of top surface of package m2
PA Percentage contribution %
Pi Mean pressure components Pa
XXII
q Convectional heat transfer energy W
qrad Radiative heat energy W
Convectional heat transfer energy per unit volume W/m3
R Universal gas constant J/mol.K
r Orifice pitch cm
ri Heat supplied externally into the body per unit volume W/m3
Position vector -
Scattering direction vector -
S Surface area m2
Total sums of squares -
Factor sums of squares -
Pure sum of squares -
Tg Temperatures of the environment K
To Initial temperature K
Ts Actual temperature of surface K
T Local temperature K or oC
Ti mean temperature K
∆T Temperature uniformity K or oC
t Time s
Ux, Uy, Uz Velocity component in x, y, z direction mm/s
Ui, Uj Mean velocity components m/s
ui, uj Turbulent velocity components m/s
Material time rate of the internal energy W
v Conveyor speed cm/s
vi Kinematic viscosity of the fluid m2/s
V Total volume of structure/solid material m3
Variance factor -
Weight of each quality characteristic -
ΔW Accumulated strain energy density per cycle of each element, MPa
MPa
XXIII
∆Wave Average accumulated strain energy density per cycle for the interface elements
PSI
x, y, z Cartesian coordinates position -
Greek Symbols
ρ Density of structure/fluid kg/m3
λ Thermal conductivity of PCB or package W/m.K
τ Time constant s
θ Turbulent temperature fluctuation K
μt/μ Turbulent viscosity ratio -
Refractive index -
Phase function -
Solid angle o
ε Strain -
Grey relation coefficients -
σs Scattering coefficient -
σ Stress Pa
Fatigue life cycles
Poison ratio -
Ө Temperature of thermal load K
Өz User-defined value of absolute zero on the temperature scale used
K
Normalized result -
Grey relation grade -
XXIV
LIST OF ABBREVIATIONS
2-D Two-dimensional
3-D Three-dimensional
AI Artificial Intelligence ANOVA Analysis of variance
ATC Accelerated Temperature Cycling
BGA Ball Grid Array
BT Bismaleimide Triazine
CFD Computational Fluid Dynamics
CR Complexity Ratio
CSP Chip Scale Packaging
CTE Coefficients of Thermal Expansion
DO Discrete Ordinates
DOE Design of experiment
DOF Degrees of freedom
DTRM Discrete Transfer Radiation Model EDM Electrical Discharge Machining EDS Energy Dispersive X-ray spectroscopy
FC Flip Chip
FDM Finite Difference Method FEA Finite Element Analysis
FEM Finite Element Method
FVM Finite Volume Method
GA Genetic Algorithm
I/O Inputs/Outputs
IC Integrated Circuits
IMC Intermetallics compounds
IR Infrared
JEIDA Japan Electronic Industries Development Association LCCC Leadless Ceramic Chip Carrier
XXV MEMS Micro-Electro-Mechanical Systems
MpCCI Mesh-based Parallel Code Coupling Interface
MSD Mean-Squared Deviation
N2 Nitrogen
NLP Nonlinear programming
NSMD Non-Solder Mask Defined PCB Printed Circuit Board
PDE Partial Differential Equations
PGA Pin Grid Array
PLCC Plastic Leaded Chip Carrier
QFP Quad Flat Pack
QP Quick Propagation
R&D Research and Development
RANS Reynolds-Averaged Navier–Stokes RMA Rosin Mildly Activated
RoHS Restriction of Hazardous Substances directive RSM Response Surface Methodology
S/N Signal- to-Noise
S2S Surface-to-Surface
SEM Scanning Electron Microcopy SIP System- in-a-package
SJ Solder Joint
SMCs Surface Mount Components
SMT Surface Mount Technology
SOIC Small Outline Integrated Circuit
TC Thermocouple
THCs Though Hole Components
THT Through Hole Technology
TPB Thermal Profiler Board TSOP Thin Small Outline Package
TSV Though Silicon Via
XXVI
UDF User Defined Function
WL-CSP Wafer Level-Chip Scale Package
WLP Wafer Level Packaging
XXVII
KAEDAH GANDINGAN HABA BAGI PROSES PEMATERIAN REFLOW
ABSTRAK
Pematerian reflow adalah salah satu faktor yang penting dalam pembangunan teknologi permukaan menempelkan, terutamanya ke arah pakej yang bebas plumbum dan pengecilan kawasan bola grid. Selain itu, profil reflow yang tidak mencukupi telah menyebabkan isu- isu kebolehpercayaan dalam proses pembuatan elektronik. Tujuan kajian ini adalah untuk membangunkan kaedah gandingan haba yang boleh digunakan untuk menyiasat tindak balas suhu dan tekana n haba di papan elektronik (di peringkat papan dan pakej) semasa proses reflow. Kaedah berangka ini terdiri daripada pengiraan aliran dalaman bagi ketuhar reflow digabungkan dengan pemanasan atau penyejukan dalam struktur papan elektronik. Mesh-based Parallel Code Coupling Interface (MpCCI) telah digunakan sebagai perisian gandingan untuk kaedah ini. Kaedah ini disahkan dengan ukuran eksperimen dan kajian sebelumnya. Dari keputusan analisis peringkat papan, kawasan sejuk dan keseragaman suhu (ΔT) semakin meningkat, apabila papan elektronik semakin rumit. Kawasan sejuk boleh berlaku di dua lokasi dalam papan elektronik. Satu kelajuan penghantar yang sesuai, 1.0 cm/s telah dipilih untuk mengekalkan ΔT di bawah 10 °C dan mengelakkan terlalu panas bagi pakej haba kritikal.
Selain itu, ciri-ciri kualiti seperti tekanan haba, suhu puncak, masa reflow dan ΔT di peringkat pakej bagi pateri plumbum telah ditentukan daripada analisis peringkat pakej, dan mempunyai satu perjanjian yang baik dengan kesilapan maksimum 6% berbanding dengan keputusan eksperimen. Kesan pematerian bebas plumbum dan penyusunan corak pateri semasa penyejukan dalam proses reflow telah dibincangkan, dan menunjukkan
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bahawa pateri bebas plumbum (SnAgCu) layak sebagai bahan penggantian untuk pateri plumbum. Selain itu, maksimum tekanan von-Mises dalam pateri dipengaruhi oleh corak susunan pateri, dan tidak dipengaruhi oleh bilangan pateri. Cadangan telah dibuat untuk meningkatkan masa patah dengan menukar corak susunan, dan telah berjaya meningkat sebanyak 49.9%. Kaedah berangka ini telah dilanjutkan dan digabungkan dengan kelabu berasaskan Taguchi untuk mengoptimumkan pematerian bebas plumbum yang mempunyai pelbagai prestasi. Gabungan hibrid ini bertujuan untuk mengurangkan kadar kecacatan pateri dalam pakej kawasan bola grid. Faktor- faktor dan ciri-ciri kualiti bagi ketuhar yang jenis kumpulan dan penghantar berterusan telah dipertimbangkan.
Taguchi ortogon telah dilakukan, dan tetapan parameter optimum untuk setiap ketuhar reflow telah ditentukan. Kedua-dua kajian kes menyatakan peringkat penyejukan dalam proses reflow bebas plumbum adalah faktor yang paling berpengaruh untuk kebolehpercayaan pateri. Keputusan ujian menunjukkan bahawa pengesahan gred hubungan kelabu telah meningkat dengan ketara sebanyak 117.4% dan 46.6% untuk Kajian kes 1 dan 2, masing- masing. Secara keseluruhannya, kaedah yang baru dibangunkan ini telah banyak mengurangkan kecacatan pateri dan memberi satu garis panduan kepada isu- isu kebolehpercayaan bagi pematerian bebas plumbum dalam industri pembuatan elektronik.
XXIX
THERMAL COUPLING METHOD FOR REFLOW SOLDERING PROCESS
ABSTRACT
Reflow soldering is one of the most significant factors in development of surface mount technology (SMT), especially toward the lead- free and miniaturization of the advanced ball grid array (BGA) package. Moreover, an inadequate reflow profile cause s the reliability issues in manufacturing assembly process. The purpose of this study is to develop a thermal coupling method that uses to investigate the temperature and thermal stress responses of electronic boards (at board and package level) during the reflow soldering process. The numerical method comprises the computational fluid modeling of the internal flow of the reflow oven and the structural heating/cooling modeling of the BGA assembly. The Mesh-based Parallel Code Coupling Interface (MpCCI) was used as the coupling software. The model was validated with experimental measurements and previous studies. From the results of board- level analysis, the cold region and temperature uniformity (ΔT) increased with increasing complexity of the electronic boards. The cold region was occurred in two possible locations on the board. A suitable conveyor speed of 1.0 cm/s was determined to maintain ΔT below 10 °C and prevent overheating of the thermally critical package. Apart from that, the quality characteristics such as the thermal stress, peak temperature, reflow time and package- level ΔT of lead- based solder were determined from the package- level analysis, and had a good agreement with maximum error of 6% compared to the experiment results. The effect of lead-free soldering and solder joint arrangements during the cooling stage of the reflow process has been discussed, and showed that the lead-free solder (SnAgCu) was
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qualified soldering material for replacement of lead-based solder. Besides, the maximum von-Mises stress of the critically affected joint was influenced by joint arrangement patterns and not by the number of solder joints. A recommendation was made to increase the fracture time by changing joint arrangement pattern, which successfully improved by 49.9%. This numerical method was extended and combined with a grey- based Taguchi method for optimizing the multiple performances of the lead-free reflow soldering process. This hybrid combination study aims to minimize the solder joint defect rate of a BGA package. Various factors and quality characteristics of batch-type and conveyor continuous-process ovens were considered. The Taguchi orthogonal array was performed, and the optimal parameter settings of each oven were determined. Both case studies expressed the cooling stage of lead- free reflow process was most influential factor to solder joint reliability. The confirmation test results showed that the grey relational grade of Case studies 1 and 2 significantly increased by 117.4% and 46.6%, respectively. On the whole, the newly developed approach greatly reduced solder joint defects and provided a design guideline to lead-free reliability issues in the electronics manufacturing industry.
1 CHAPTER 1 INTRODUCTION
1.1 Surface mount technology
Printed circuit board (PCB) assembly is necessary part of the manufacturing process, in which either the surface mount technology (SMT) or through-hole technology (THT) used to attach the components onto the pads of the PCB. SMT is a radical transformation from THT that enables the progressing of the electronic industry toward the trends of miniaturization, denser, high speed, and lower cost (Lee, 2002).
During the late 1970s, the interest of SMT has been rapidly increased and recognized by electronic industries due to the difficulties of THT in handling the higher component densities on PCB. More cost is needed for THT to drill more holes for an increasing number of leads of component. Moreover, there have a difficulty of drilling smaller holes for pitch dimensions that smaller than 0.1 inch at that time technology (Lee, 2002).
Thus, the SMT is introduced with the benefits of higher degree of automation, smaller volume with higher density, lower cost and better per formance. The examples of lead or leadless components on the surface of PCB of SMT and THT are shown in Figure 1.1. However, the THT is still commonly used for high-power devices because the through-hole connector has additional strength to attach the component (Backwell, 2006). Three types of classification of PCB assembly normally addressed by manufacturer, in which Type I boards have surface mount components (SMCs) only for both sides, Type II boards have both SMCs and though-hole components (THCs) on one side of the board and passive components on the other side and Type III boards have
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THCs on one side of the board and passive components on the other side (Backwell, 2006).
Figure 1.1: Types of PCB assembly technology (a) SMT (b) THT (Lee, 2002) SMCs can exist in the form of capacitor, resistor, transistor, discrete semiconductor, inductor, and integrated circuit (IC). The structure of IC is more complex when compared to other passive SMCs (end-terminations designed), which normally supplied in a variety of packages, such as small-outline integrated circuit (SOIC), thin small-outline package (TSOP), plastic leaded chip carrier (PLCC), leadless ceramic chip carrier (LCCC), quad flat pack (QFP), and ball grid array (BGA) package.
A good overview of various styles of a package can be found in the most semiconductor manufacturer website (Toshiba, 2012).
Moreover, there have five major categories of solder joint configuration for the IC packages, as shown in Figure 1.2. The Gullwing leads (Figure 1.2 (a)) are particularly used in the case of fine-pitch applications. However, these leads are easily disposed to bend or sweep when in handling the package. Butt- leads (Figure 1.2 (b)) are easier to manufacture when compare to the gullwing leads, but they are faced a low performance in solder joint reliability. The J-lead design, as shown in Figure 1.2 (c) has
(a)
(b)
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some difficulties in rework, inspection, and lead- forming. Besides, the solder joint reliability for leadless metallization, as shown in Figure 1.2 (d), often affected by the mismatch of coefficients of thermal expansion (CTE) of the various materials in the package. Moreover, these joint configurations (Figure 1.2 (a-d)) give a low standoff of the package, which cause the poor clean of flux residue at the area underneath the package (Lee, 2002).
Figure 1.2: Package lead configurations (a) Gullwing (b) Butt- lead (c) J- lead (d) Leadless metallization (e) Ball- lead (Lee, 2002)
In spite of these challenges, the grid array packaging that mainly driven by the demand toward finer pitch, and provides higher inputs/outputs (I/O) density together with easier manufacturability, better solder joint reliability, and higher standoff was introduced at mid 1990s (Eric, 1997; Koch, 1998). BGA package that uses the ball- lead
(a) (b)
(c) (d)
(e)
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is one of the examples of the joint configuration, as shown in Figure 1.2 (e). Apart from that, the cross-section of plastic BGA package is illustrated in Figure 1.3 (Mawer, 1996).
The I/O from a silicon die is connected to BT/Glass substrate via wire bonding or flip chip technique. Then, it is redistributed through the BGA substrate to an area array pattern at the bottom side of a package which is bumped with lead-based (SnPb) or lead- free (SnAgCu) solder balls. After that the package is connected to the BGA pads in PCB through the reflow soldering process (Mawer, 1996).
Figure 1.3: Schematic diagram of Plastic BGA (Mawer, 1996)
BGA technologies have been rapidly accepted and growth by the electronic industry, as reported by Lee (2002). Lee (2002) was reported that an optimistic estimate of the BGA market was 500 million units in 1997 and 920 million units in 2000. This illustrates that the BGA market demand will continue growth in the future trend.
Moreover, the ultimate goal of having package that reduces to die size with more advance functions, the next forecast until 2015 was though-silicon via (TSV), micro- electro-mechanical systems (MEMS) and three-dimensional (3-D) packaging integration
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design that using BGA as a footprint to connect the routing channels of the circuit board (Toshiba, 2012). Thus, the BGA packaging has a deep impact on future SMT.
1.2 Surface mount assembly and challenges
There are three types of method that the SMCs and THCs can be attached onto PCB, such as a wave soldering, reflow soldering, and conductive adhesive curing processes. However, the use of conductive adhesive is not common, and only applied in some flexible circuit boards with heat sensitive component (Lee, 2002). Moreover, the Type II and Type III boards require adhesive to mount the SMCs for pass through the wave soldering (Backwell, 2006). Wave and reflow soldering are the two common soldering process involved in PCB assembly. The wave soldering is a large-scale soldering process used in THCs assemblies. Typically, PCBs with THCs inserted are pre-fluxed via a foam fluxer and then passed over a dual solder wave for soldering, as shown in Figure 1.4. However, it has always been the bottleneck for wave soldering of SMCs that the starved solder joints and bridging defect problems are found.
Figure 1.4: Schematic of the wave-soldering process (Tarr, 1999)
Thus, the reflow soldering is introduced to overcome these problems. The preparatory steps of reflow soldering involve screen printing of solder paste to the PCB bond pads, followed by the placement of SMCs on the solder paste deposit. Next, the
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PCB assembly is subjected to controlled heat in the reflow ovens, which melt the solder paste and solder balls and permanently form the joint. The controlled heat in a reflow oven is programmed according to the reflow thermal profile (Koch, 1998). The reflow soldering was quickly become the main stream in PCB assembly technology when compared with the wave soldering, due to higher yield, throughput, and reliability (Lee, 2002).
The quality of peripheral lead is easily inspected and reworked with a fine tip soldering iron after reflow soldering process, but cannot be applied on BGA rework due to the tip soldering iron not possible access the internal array of BGA solder joints. Thus, the lack of ability of inspection is limiting the early growth of BGA technology. The modified procedures of reflow soldering for BGA package were introduced by early works of pioneer semiconductor company, such as IBM, Motorola, and Compaq (Eric, 1997). However, the margin of BGA solder joint and pitch dimensions in packaging technology are continually scaled down as a future trend, which leads to more complex thermal responses when the PCB assembly passes through the reflow oven (Schüßler et al., 2009). A loss of productivity of 30-50% of the total manufacturing costs was stated by Tsai (2012b) for the additional repair and rework of defective products. Thus, many challenges regarding to the reflow soldering of BGA package were needed to be overcome. The optimization of its performance was important to enhance the solder joint reliability issues.
1.3 Proble m statement
Reflow soldering is one of the most significant factors in determining the solder joint defect rate (Tsai, 2012b). The traditional methods to obtain the reflow thermal
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profiles are based on experimental destructive measurements and some rules-of-thumb (Su et al., 1997). However, there are difficulty in measuring the temperature for fine pitch dimensions of a package. The temperature that was measured using the thermocouple was examined only at the substrate of assembled PCB. The actual temperature of a solder joint remained unknown. Moreover, the experimental trial-and- error technique is time-consuming and very expensive. For examples, a full qualification of new product may take up to six months of testing time (van Driel et al., 2007). So, it urgently needs new solutions to analyze the performances of the soldering process.
A simulation tool for the thermal response of solder joint and flow field prediction of a reflow process was started emerged at 1998s (Bailey et al., 1998; Kim et al., 1998). Modeling and simulations of the reflow process were provided with more information on the particular process and help the electronic manufacturing industry to solve reliability issues. Shen et al. (2005; 2006) and Inoue and Koyanagawa (2005) built the Finite Element Method (FEM) model to obtain the temperature distribution of a BGA package for the reflow process. The average heat-transfer coefficient was calculated using experimental equations for multiple impinging jets. However, the proposed method cannot be dealt with the changes of some parameters in a reflow oven (e.g. the velocity and density of the gas). Baated et al. (2010) reported that the solder joint reliability was strongly affected by process atmosphere during the reflow process.
Moreover, the experimental results obtained by Illés (2010a; 2010b) also showed that the heat-transfer coefficient (h) was inconsistent within the reflow oven. The accuracy of prediction of the thermal response at initial stage of numerical modeling was limited by the computer power and software ability.
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Therefore, with the growing trend of computer power and software ability, the proposed technique was aimed to implement a thermal coupling method, which internal flow of a reflow oven was modeled in Computational Fluid Dynamics (CFD) software, while the structural heating or cooling BGA package simulation was done using FEM software. The Mesh-based Parallel Code Coupling Interface (MpCCI) was utilized as a code coupling of both commercial's software. The thermal profiling experiments and previous studies were used to validate the simulation method. This work is expected to provide a new guideline by introducing the thermal coupling simulation method for reflow soldering process in BGA assembly. Parametric studies regarding oven parameter setting, board and package configurations were performed using such method.
Additional challenge was presented with environmental concerns propelling a rising trend toward lead- free soldering (Yang et al., 2001). The Restriction of Hazardous Substances directive (RoHS) banned the intentional addition of lead-bearing solder to consumer electronic parts produced start from 1st July 2006 (Stoyanov et al., 2009;
Baated et al., 2010). An alternative lead-free solder such as SnAgCu solder was recognized as a replacement for conventional lead-based SnPb solder (Baated et al., 2010). This type of lead- free solder required a narrower range of flow temperature and workable melt compared with a lead-based solder. Hence, the present study is focused on investigate the effect of lead- free soldering on the reliability issues.
Apart from that, the reflow soldering process can be divided into four stages, namely as, preheating, soaking, reflow and cooling stages. Each stage of the reflow process has its impact on the solder joint defect. Tsai (2012a) stated that advance optimization approach provided a more cost-effective way, and solder joint defect can
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be detected earlier in the manufacturing process. According to the production experts, the performance of reflow soldering process was determined by several quality characteristics, such as, thermal uniformity, reflow time, thermal stress generated and peak temperature of a solder joint. In order to minimize the solder joint defect of lead- free BGA package, a well-designed optimization methodology is described in the present study to improve the multiple quality characteristics of lead- free reflow soldering.
1.4 Objectives of the study
Against the investigated background of the reflow soldering process for BGA application, the specific objectives of the thesis study are as follows:
1 To implement the thermal coupling method at board- level PCB assembly under influenced of process atmosphere, and visualize the flow characteristics of reflow oven.
2 To perform the thermal coupling method at package- level BGA assembly, and predict the quality characteristics of the reflow process in a specific solder joint.
3 To conduct an experimental thermal profiling for verifying the thermal response s of the numerical model for lead-based and lead-free soldering process.
4 To investigate the reflow oven parameter setting, board configurations and solder materials, and how they affect the performances in terms of the temperature and thermal stress of solder joints.
5 To optimize the lead- free reflow soldering process for BGA package family with multiple quality characteristics, and run the confirmation test at initial and optimal conditions.
10 1.5 Scope of the research work
In this research work, the investigation of temperature and thermal stress within the PCB and solder joints are focused on the reflow soldering process through the simulation and experiment. The simulation (thermal coupling method) of fluid flow and structural analyses concentrates on the BGA assembly by performing two streams of analysis: one towards overall board- level analysis, and the other towards a package- level analysis. The validation of the numerical method was performed with the thermal profiling experiment and the study obtained by the previous researchers. This research also focused on the parametric case studies to enrich the understanding of board configurations, reflow oven parameter setting and solder materials. Moreover, the optimization of the lead- free reflow soldering using grey-based Taguchi methodology was carried out to investigate the interactive relationship of the factors to minimize the solder joint defect in the reflow soldering process. The basic idea underlying in the optimization methodology was such that the combination of the concept of design of experiment (DOE) and grey relational system, which was applied to solve multiple quality characteristics of lead- free reflow soldering process.
1.6 Contribution of study
Malaysia’s electronics industry has certainly come a long way over the last 40 years. The electronics industry is the primary sector in Malaysia's manufacturing sector, which contributing significantly to the country's manufacturing output (29.3 %), exports (55.9 %) and employment (28.8 %) (investPenang, 2009). In these 40 years, electronics industry helps Malaysia's transformation from a third-world country becomes a semi- developed country. Moreover, the worldwide sales of semiconductors reached US$ 24.4
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billion in May 2012, up to 1.4% from April 2012's sales of US$ 24.1 billion (Rosso, 2012). These examples show the power of the electronics industry to the worldwide economic and country.
The tendency to decrease the size of electronic packages with higher-density I/Os, leads to the use of area array packages, such as BGA packaging, chip scale packaging (CSP), flip chip (FC), and wafer level packaging (WLP) technologies.
Moreover, TSV, MEMS, 3-D packaging that using a BGA as a footprint are possible solutions in die packaging for next IC revolution. Most semiconductor companies turn to the lead- free soldering process as legislation driven by environmental concerns. The multi- national companies, such as Motorola and Intel paid great attention to the lead- free reliability of solder joints and the assembly yield of the surface mounting process as the use of advanced “green” electronic packaging technology has increased.
With the successful in present research, the cost of the research and development (R&D) of a modern package was greatly reduced by saving the time and material cost.
This will also reduce the cost of product and increases the profit of the company.
Moreover, these findings provide new simulation guidelines (thermal coupling method) at the board and package levels that influenced by process atmosphere. These guidelines were very useful for the accurate control of temperature and thermal stress distributions within components and printed circuit boards, which was one of major requirements to achieve high reliability of electronic assemblies.
The optimization techniques with multiple quality characteristics adopted in the present study provided the guideline to determine the optimal setting of a reflow oven
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that minimized the solder joint defect and enhanced the reliability issues. With the data presentation in this research, it has laid a better fundamental understanding and foundation for future research works to implement optimal reflow soldering process in modern packaging.
1.7 Thesis outline
This thesis contains five chapters, including the introduction as Chapter 1. In Chapter 1, brief presentation about SMT, problem statement, contribution of study, objectives and scope of research have been introduced. Detail literature reviews of BGA technology, reflow soldering process, modeling and optimization methods regarding the reflow process are presented in Chapter 2. In Chapter 3, the proposed methodology of thermal coupling method and optimization technique is highlighted. The experimental setup for thermal profiling and confirmation test for initial and optimal setting is included in Chapter 3. In Chapter 4, parametric studies on the reflow oven setting, board configurations and solder materials in terms of the temperature and thermal stress have been investigated. Several quality characteristics and optimal conditions of reflow soldering process on BGA assembly are simulated and presented in Chapter 4. Lastly, the conclusions drawn from the research presented in this thesis are given in Chapter 5, and a few suggestions for future research are identified.
13 CHAPTER 2 LITERATURE REVIEW 2.1 Introduction
The technologies of the electronic product towards more complicated and miniaturization, the margin of solder joint and pitch dimensions in electronic component is continually scaled down as a future trend. These challenges lead to more complex thermal responses when the PCB assembly passes through the reflow oven. Additional challenge is presented with environmental concerns propelling a rising trend toward lead-free soldering. Lead- free solder requires a narrower range of flow temperature and workable melt compared with a lead-based solder. Thus, there is an urgent need for researcher to seek for innovative solutions to analyze and optimize the performance of soldering process for modern packaging. In this chapter, substantial previous works related to basic information of the reflow soldering process will be reviewed.
Furthermore, before discussing the work in the literature related to the modeling and optimization of reflow soldering process, an overview of the ball grid array technology is presented in next section.
2.2 Ball Grid Array (BGA) technology
The demand of portable electronic devices such as tablet computers, laptop, computers, and smart phones is in exponent growing trends. This leads to urgent need for packaging solutions that enable fulfill the customer needs and meet market demands for today and in the future. Since the mid 1990s, the grid array packaging has captivated the electronic industry and gained rapid acceptance due to its denser packing of
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functionality, higher performance, and lower cost, which as shown in Figure 2.1. BGA and CSP are examples of the grid array packaging have been created to support the high- density wiring technology in SMT (Eric, 1997). Moreover, the miniaturization forced the future trends to create new approaches in die packaging in order to achieve the highest performance.
The TSV, MEMS and 3-D packaging are possible solutions in die packaging for next IC revolution, as shown in Figure 2.1 (Toshiba, 2012). Unlike the 3-D packaging (die stacking) which using the wire bonds, the new design system- in-a-package (SIP) using a passive TSV interposer for high performance was created (Lau, 2011). Agonafer et al. (2008) and Lau (2011) stated that the thermal management and reliability issue were the major concern in that modern packaging. Agonafer et al. (2008) also reported that finite element analysis was useful during the design and deve lopment of the 3-D packaging or die stacking.
Figure 2.1: Roadmap of BGA Technology (Toshiba, 2012)
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Besides, near all the future roadmap of new packaging technologies will use a BGA as a footprint to connect to the routing channels of the circuit boards. Thus, the BGA packaging has a deep impact on future packaging technology. There were three categories of BGA families based on the substrate material used to fabricate them (Eric, 1997). The examples of cross-section of each BGA families are shown in Figure 2.2.
Figure 2.2: The BGA Families (a) Plastic BGA (b) Ceramic BGA (c) Tape BGA (Eric, 1997; Mawer, 1996)
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The suitable substrates for Plastic BGA are Polyimides, Bismaleimide Triazine (BT) epoxy glass and Dry-Clad. The example of a PBGA package manufacturing flow chart is shown in Figure 2.3 (Eric, 1997). Besides, the alumina is conventionally used as the material choice for Ceramic BGA. The advantages of PBGA are due to its low-cost and CTE of substrate is well matched with assembly board compare to the CBGA. But, the typical “popcorn” cracking (Sung and Kam, 1998; Backwell, 2006) or delamination problems (van Driel et al., 2007) in PBGA were eliminated with CBGA because CBGA had no moisture sensitivity. The third type of BGA is Tape BGA. The copper heat spreader acts as the base to which the flex tape is laminated. The advantages of TBGA are the excellent thermal performance and able to achieve fine line's interconnection.
Fabricate package substrate in panel or strip form
Ni/Au plate top and bottom pads
Die attach with silver epoxy
Thermo-compression wirebond chip
Over mold encapsulate chip
Apply flux or solder paste to package
Place solder balls near fixture for packaging
Reflow solder balls to package
Clean and singulate packages from panel or strip
Figure 2.3: PBGA assembly process (Eric, 1997)
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Furthermore, for each of BGA families can be used in different d ie packaging, which single chip or multiple chips, single layer or stacked layers and wire bonding or flip chip. The array of solder balls can be filled or partial filled, which has shown in Figure 2.4. All the variety of the same BGA families is depended on the manufacturer, customer needs and performance requirements.
Figure 2.4: Filled array and partially filled BGA packages (Eric, 1997) The CSP is defined as the package area no greater than 1.2 times of the chip area, and it must be a single chip and direct surface mountable package with ball pitches no more than 1 mm. The examples of CSP that use a double sided substrate very similar to the PBGA assembly, with the chip wire bonded or flip chip (C4) on the top surface, are shown in Figure 2.5. An example of cross-section of flip chip CSP is shown in Figure 2.6. The gap of solder joints between chip and substrate is filled by an underfill to increase the fatigue life of the solder joints. The CSP also called as wafer- level chip- scale package (WL-CSP) or a WLP.
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Figure 2.5: Amkor CSP Devices (Eric, 1997)
Figure 2.6: Cross-section of CSP (Lau, 1997) 2.3 Reflow soldering process
The reflow soldering process is the assembly process of attaching SMCs to PCB.
The surface mount assembly of BGA package is slightly different from that tradition assembly of QFP. The peripheral leads of QFP are easily reworked with a fine tip soldering iron, but this technique cannot apply on BGA rework. Thus, the lack of ability of inspection is limiting the early growth of BGA technology (Lee, 2002). However, the problems were solved by early work of pioneer semiconductor companies (IBM,
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Motorola, and Compaq). The standard procedures involve in reflow soldering are shown in Figure 2.7.
Figure 2.7: Reflow soldering process
The preparatory steps involve screen printing of solder paste to the PCB bond pads. A stencil is used in the solder paste print operation to act as a template for the land pattern. Then, the actuated squeegee blade impacts and generates hydrodynamic pressure simultaneously for both rolling and translational motion on the bulk solder paste positioned in front of the squeegee, as illustrated in Figure 2.8 (Amalu et al., 2011). The PCB is then separated from the stencil, leaving paste deposits on the PCB pads. Alternative method involves the dispensing process that deposits the solder paste by forcing the paste through a needle for paste registration and volume control. The dispensing process is very suitable for addressing the needs of reflow soldering on a non-flat surface (Lee, 2002). The random visual inspection was performed after the printing process.
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Figure 2.8: Stencil printing process
For better understanding the solder joint formation, the elements of solder paste were discussed. The solder paste used for SMT soldering consists of the mixture of microscopic solder balls, flux, activator and solvents. The fluxes in solder paste are important part of solder paste, which available in water-soluble, rosin mildly activated (RMA) and no-clean. No-clean fluxes have a less abilities to reduce the oxides that formed in paste metal balls and substrate metallization (Backwell, 2006), but low production cost due to the cleaning section is eliminated. The guide for choosing the correct solder paste was needed from the supplier, which regarding to the customer requirements.
Next, the modern placement machines have vision systems that are able to place the BGA packages with high accuracy (Koch, 1998). The placement offset is checked when setting up the assembly. If components place improperly, misalignment may occur. However, if misplacement is minimal, surface tension has a tendency to realign the components at the center of the solder during the reflow soldering process.
(a)
(b)
Printed Circuit Board
Printed Circuit Board
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Then, the PCB assembly is subjected to controlled heat in a reflow oven, which melts, reflows, solidifies, and finally permanently forms the joint (Koch, 1998). The controlled heat in a reflow oven is programmed according to the reflow thermal profile, and will be discussed in details at Section 2.3.1. Reflow defects like voids, bridging, splashing, and cold joints, which occur at an assembly are discovered at visual inspection after the soldering process (Lee, 2002). Moreover, real-time X-ray systems are used during the reflow process for inspecting voids, opens and skewed solder joints.
Besides, any electrical defects from the soldering process are discovered at In-Circuit Test or Functional Examination Test.
After solder joint inspection and examination, the BGA rework or repair is performed using the rework station. For rework, the heating BGA package is localized using a hot air nozzle. Next, the damage BGA package is lifted with vacuum head and replace with new BGA on the board, and then followed by reflow and inspection process for that BGA package (Eric, 1997).
2.3.1 The reflow oven
Currently, there are two types of reflow oven, batch-type and conveyor continuous-process oven, which depends on the production volume required. However, the reflow oven can also be classified based on the heat-transfer mechanism. Three modes of heat transfer mechanism: conduction, convection or radiation normally utilized by oven manufacturer (Holman, 2002). While many early ovens were of the vapor phase type, most commonly ovens used today were infrared (IR) reflow, forced convection reflow and combination of the two (Backwell, 2006). The IR reflow oven employs IR
