Therefore, various transformerless PV inverters topologies are proposed recently to reduce the leakage current to meet the requirement of the standard

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(1)Abstract Small, highly efficient and low cost photovoltaic (PV) system can be achieved when the transformer is removed from the PV inverter. Nevertheless, transformerless PV inverters generates dangerous leakage currents. Therefore, various transformerless PV inverters topologies are proposed recently to reduce the leakage current to meet the requirement of the standard. In this project, two types of recently proposed transformerless PV inverters are investigated, i.e., single-phase and three-phase inverters. A common-mode model circuit for each type is developed to study the common-mode behavior of the transformerless PV inverters. It is shown that the leakage current is directly depending on the commonmode voltage (CMV). Based on the analysis of the studies, a novel transformerless PV inverter topology is proposed for both single-phase and three-phase PV systems respectively. For single-phase PV systems, a simple modified H-bridge zero-voltage state rectifier (HBZVR-D) is proposed to eliminate the leakage current. A fast-recovery diode is added to the existing HBZVR topology to improve the clamping branch performance. It is shown that the improved clamping branch of the proposed topology completely clamps the CMV to constant to eliminate the leakage current. On the other hand, a three-phase transformerless inverter (H7), adapted from the single-phase H5 topology, is investigated. An additional switch is added to the conventional full-bridge structure to provide galvanic isolation. Here, a novel modulation technique based on conventional discontinuous pulsewidth modulation is proposed. It is shown that the proposed topology is able to reduce the CMV in order to reduce the leakage current. The validity of the proposed inverters are verified via simulations and laboratory prototypes. DSP TMS320F28335 is used to program the modulation techniques. The iii.

(2) performances of the proposed topologies, in terms of CMV, leakage current, total harmonic distortion (THD) and efficiency, are compared with various recently proposed transformerless PV inverters. It is experimentally proven that the proposed transformerless single- and three-phase inverters are able to reduce the leakage current with superior overall performance among the recently proposed topologies.. iv.

(3) Abstrak Sistem photovoltaic (PV) yang ringan, berkecekapan tinggi dan berkos rendah boleh dicapai apabila transformer dikeluarkan dari penyongsang PV. Walau bagaimanapun, penyongsang PV tanpa transformer menjana arus bocor yang berbahaya. Oleh itu, pelbagai topologi penyongsang PV tanpa transformer dicadangkan baru-baru ini untuk mengurangkan arus bocor untuk memenuhi piawaian. Dalam projek ini, dua jenis penyongsang PV tanpa transformer yang baru-baru ini diusulkan akan disiasat, iaitu, penyongsang PV fasa tunggal dan tiga fasa. Satu model mod sama digunakan untuk mengkaji tingkah laku mod sama sistem PV tanpa transformer. Ia menunjukkan bahawa arus bocor bergantung secara langsung kepada voltan mod sama (CMV). Berdasarkan analisis kajian, suatu topologi penyongsang PV tanpa transformer yang novel telah diusulkan untuk sistem PV fasa tunggal dan juga tiga fasa. Bagi sistem PV fasa tunggal, “H-bridge zero-voltage state rectifier” (HBZVR-D) telah dicadangkan untuk menghapuskan arus bocor. Diod cepat-pulih ditambah kepada topologi HBZVR yang sedia ada untuk meningkatkan prestasi cabang pengapitan. Ia menunjukkan bahawa cabang pengapitan HBZVR-D yang dicadangkan dapat mengapit CMV untuk menjadikannya malar supaya dapat menghapuskan arus bocor. Selain itu, penyongsang tiga fasa (H7), yang diubahsuaikan daripada topologi fasa tunggal H5, turut disiasat. Suis tambahan diintegrasikan kepada struktur tetimbang penuh konvensional untuk mewujudkan pengasingan galvanik. Di sini, teknik novel pemodulatan berdasarkan pemodulatan lebar denyut tidak berterusan konvensional telah dicadangkan.. Ia. menunjukkan. bahawa. topologi. yang. dicadangkan. mampu. mengurangkan CMV untuk mengurangkan arus bocor. Kesahan penyongsang yang dicadangkan disahkan melalui simulasi dan prototaip makmal. DSP TMS320F28335 digunakan untuk memprogram teknik v.

(4) pemodulatan. Prestasi topologi yang dicadangkan itu, dari CMV, arus bocor, herotan harmonic seluruh (THD) dan kecekapan, dibandingkan dengan pelbagai penyongsang pengubah PV yang dicadangkan baru-baru ini. Uji kaji telah membuktikan bahawa penyongsang PV fasa tunggal dan tiga fasa yang dicadangkan dapat mengurangkan arus bocor dengan prestasi keseluruhan yang unggul antara topologi baru-baru ini dicadangkan.. vi.

(5) Acknowledgement. I would like to praise and thank the Almighty God by giving me the opportunity to successfully complete this thesis in fulfillment of the requirement for the Doctor of Philosophy in Electrical Engineering.. I wish to express my gratitude to my supervisor, Professor Dr. Nasrudin Abd Rahim and Professor Dr. Hew Wooi Ping for their constructive advice and guidance, which have undoubtedly motivate me throughout my research.. I also would like to thank all staffs in the UM Power Energy Dedicated Advanced Centre (UMPEDAC) particularly Dr. Che Hang Seng and my colleagues Tan Chin Yew, Lee Jhee Fong, Siti Rahimah and Farihah Shariff for their support and encouragement.. Also, not forgetting my church members and friends, who are praying and supporting me all the time. Last but not least, my sincere gratitude goes to my family and my girlfriend, Lee Soo Yee, who never fail to support and motivate until the completion of this thesis.. vii.

(6) Table of Contents Contents. Abstract. iii. Abstrak. v. Acknowledgement. vii. List of Figures. xi. List of Tables. xv. List of Symbol and Abbreviations. xvi. Chapter I: Introduction 1.1 Background. 1. 1.2 Universal Inverter Prototype. 4. 1.3 62150H Programmable DC Power Supply. 7. 1.4 TMS320F28335 DSP. 7. 1.5 VDE 0126-1-1 Standard. 8. 1.6 Research. 9. 1.7 Research Methodology. 9. 1.8 Scope of Work. 10. 1.9 Outline. 11. Chapter II: Common-Mode Model: An Overview 2.1 Introduction. 12. 2.2 Common-Mode Model for Single-Phase PV Systems. 13. 2.3 Common-Mode Model for Three-Phase PV Systems. 17. 2.3 Conclusion. 20 viii.

(7) Chapter III: Transformerless PV Inverters: An Overview 3.1 Introduction. 21. 3.2 Single-Phase Transformerless PV Inverters. 22. 3.2.1 Full-Bridge Inverter. 22. 3.2.1.1 Unipolar PWM. 23. 3.2.1.2 Bipolar PWM. 24. 3.2.2 Recently Proposed Transformerless Inverter Topologies. 25. 3.2.2.1 H5 Inverter. 26. 3.2.2.2 HERIC Inverter. 28. 3.2.2.3 H6 Inverter. 30. 3.2.2.4 oH5 Inverter. 32. 3.2.2.5 HBZVR Inverter. 34. 3.2.3 Leakage Current Reduction Method. 36. 3.2.3.1 Galvanic Isolation. 37. 3.2.3.2 CMV Clamping. 40. 3.3 Three-Phase Transformerless PV Inverters. 41. 3.3.1 Modulation Techniques. 43. 3.2.3.1 AZPWM. 45. 3.2.3.2 NSPWM. 47. 3.2.3.3 RSPWM. 49. 3.3.2 Converter Structures. 51. 3.4 Conclusion. 54. Chapter IV: Proposed Single-Phase Transformerless PV Inverter 4.1 Introduction. 55. 4.2 Structure of Proposed Topology. 56. 4.3 Operation Modes and Analysis. 57 ix.

(8) 4.4 Operation Principles of Improved Clamping Branch. 62. 4.5 Matlab Simulation. 63. 4.5.1 Output Performance. 70. 4.5.2 Common-Mode Behaviour. 72. 4.5.3 Losses Analysis. 79. 4.6 Experimental Results. 83. 4.7 Conclusion. 95. Chapter V: Proposed Three-Phase Transformerless PV Inverter 5.1 Introduction. 96. 5.2 Proposed MDPWM. 97. 5.3 Operation of H7 Conversion Structure. 102. 5.4 Scalar Implementation of MDPWM. 105. 5.5 Performance Analysis of MDPWM. 106. 5.5.1 Simplicity of Design and Cost. 106. 5.5.2 Line to Line Output Voltage Pattern. 107. 5.5.3 Voltage Linearity. 107. 5.6 Matlab Simulation 5.6.1 Simulation Results. 108 112. 5.7 Experimental Results. 119. 5.8 Conclusion. 129. Chapter VI: Conclusion 6.1 Concluding Remarks. 130. 6.2 Future Works. 132. REFERENCES. 133. PUBLICATIONS. 138. APPENDIX: Hardware Set Up. 139 x.

(9) List of Figures Figure 1.1: Single-phase universal transformerless topologies. 5. Figure 1.2: Three-phase universal transformerless topologies. 6. Figure 2.1: Resonant circuit for single-phase transformerless PV inverter. 13. Figure 2.2: Simplified resonant circuit for single-phase transformerless topology. 14. Figure 2.3: Simplest resonant circuit for single-phase transformerless topology. 16. Figure 2.4: Resonant circuit for single-phase transformerless PV inverter. 17. Figure 2.5: Simplified resonant circuit for three-phase transformerless topology. 18. Figure 2.6: Simplest resonant circuit for single-phase transformerless topology. 19. Figure 3.1: Full-bridge inverter. 22. Figure 3.2: Unipolar modulation. 23. Figure 3.3: Bipolar modulation. 24. Figure 3.4: H5 inverter. 27. Figure 3.5: Switching pattern for H5 inverter. 27. Figure 3.6: HERIC inverter. 29. Figure 3.7: Switching pattern for HERIC inverter. 29. Figure 3.8: H6 inverter. 31. Figure 3.9: Switching pattern for H6 inverter. 31. Figure 3.10: oH5 inverter. 33. Figure 3.11: Switching pattern for oH5 inverter. 33. Figure 3.12: HBZVR inverter. 35. Figure 3.13: Switching pattern for HBZVR inverter. 35. Figure 3.14: Universal transformerless topologies. 38. Figure 3.15: Conduction mode for dc-decoupling topology. 39. Figure 3.16: Freewheeling mode for dc-decoupling topology. 39. Figure 3.17: Three-phase full-bridge inverter. 41 xi.

(10) Figure 3.18: Voltage vector states for RCMV-PWM methods with different way of portioning the space vectors: (a) Type A and (b) type B. 43. Figure 3.19: Switching pattern, line-to-line output voltages and CMV for AZPWM. 46. Figure 3.20: Switching pattern, line-to-line output voltages and CMV for NSPWM. 48. Figure 3.21: Switching pattern, line-to-line output voltages and CMV for RSPWM. 50. Figure 3.22: Three-phase inverter with split capacitor topology. 52. Figure 3.23: Three-phase inverter with freewheeling path. 53. Figure 4.1: The conversion structure of the proposed HBZVR-D topology. 56. Figure 4.2: Switching pattern of the proposed HBZVR-D topology. 57. Figure 4.3: Mode 1 – conduction mode during positive half cycle. 60. Figure 4.4: Mode 2 – freewheeling mode during positive half cycle. 60. Figure 4.5: Mode 3 – conduction mode during negative half cycle. 61. Figure 4.6: Mode 4 – freewheeling mode during negative half cycle. 61. Figure 4.7: Simulation setup for H5 topology. 64. Figure 4.8: Simulation setup for HERIC topology. 65. Figure 4.9: Simulation setup for oH5 topology. 66. Figure 4.10: Simulation setup for H6 topology. 67. Figure 4.11: Simulation setup for HBZVR topology. 68. Figure 4.12: Simulation setup for HBZVR-D topology. 69. Figure 4.13: Line-to-line output voltage (top) and grid current (bottom) for H5 topology. 70. Figure 4.14: Line-to-line output voltage (top) and grid current (bottom) for HERIC topology. 70. Figure 4.15: Line-to-line output voltage (top) and grid current (bottom) for oH5 topology. 71. Figure 4.16: Line-to-line output voltage (top) and grid current (bottom) for H6 topology. 71. Figure 4.17: Line-to-line output voltage (top) and grid current (bottom) for HBZVR topology. 71 xii.

(11) Figure 4.18: Line-to-line output voltage (top) and grid current (bottom) for proposed HBZVR-D topology 71 Figure 4.19: VAN (top), CMV (middle), and VBN (bottom) for H5 topology. 73. Figure 4.20: Leakage current for H5 topology. 73. Figure 4.21: Microscopic waveform - VAN (top), CMV (middle), and VBN (bottom) for H5 topology 73 Figure 4.22: VAN (top), CMV (middle), and VBN (bottom) for HERIC topology. 74. Figure 4.23: Leakage current for HERIC topology. 74. Figure 4.24: Microscopic waveform - VAN (top), CMV (middle), and VBN (bottom) for HERIC topology 74 Figure 4.25: VAN (top), CMV (middle), and VBN (bottom) for oH5 topology. 75. Figure 4.26: Leakage current for oH5 topology. 75. Figure 4.27: VAN (top), CMV (middle), and VBN (bottom) for H6 topology. 76. Figure 4.28: Leakage current for H6 topology. 76. Figure 4.29: VAN (top), CMV (middle), and VBN (bottom) for HBZVR topology. 77. Figure 4.30: Leakage current for HBZVR topology. 77. Figure 4.31: VAN (top), CMV (middle), and VBN (bottom) for HBZVR-D topology. 78. Figure 4.32: Leakage current for HBZVR-D topology. 78. Figure 4.33: Simulated losses results at 1 kW prototype. 81. Figure 4.34: Experimental setup. 83. Figure 4.35: Output voltage (CH1) and output current (CH4) for H5. 85. Figure 4.36: Output voltage (CH1) and output current (CH4) for HERIC. 85. Figure 4.37: Output voltage (CH1) and output current (CH4) for H6. 86. Figure 4.38: Output voltage (CH1) and output current (CH4) for oH5. 86. Figure 4.39: Output voltage (CH1) and output current (CH4) for HBZVR. 87. Figure 4.40: Output voltage (CH1) and output current (CH4) for HBZVR-D. 87. Figure 4.41: VAN (CH1), CMV (M), VBN (CH2) and leakage current (CH4) for H5. 89. Figure 4.42: VAN (CH1), CMV (M), VBN (CH2) and leakage current (CH4) for HERIC 89 xiii.

(12) Figure 4.43: VAN (CH1), CMV (M), VBN (CH2) and leakage current (CH4) for H6. 90. Figure 4.44: VAN (CH1), CMV (M), VBN (CH2) and leakage current (CH4) for oH5. 90. Figure 4.45: VAN (CH1), CMV (M), VBN (CH2) and leakage current (CH4) for HBZVR. 91. Figure 4.46: VAN (CH1), CMV (M), VBN (CH2) and leakage current (CH4) for HBZVR-D. 91. Figure 4.47: Measured efficiency for different topologies. 92. Figure 5.1: Switching pattern, corresponding line-to-line output voltages and CMV for MDPWM in A1 ∩ B1 100 Figure 5.2: Switching pattern, corresponding line-to-line output voltages and CMV for MDPWM in A1 ∩ B2 101 Figure 5.3: H7 conversion structure. 102. Figure 5.4: Simplified equivalent circuit of H7 inverter during (a) active vectors and (b) zero vectors in region A1 ∩ B1. 103. Figure 5.5: Proposed PWM modulator. 105. Figure 5.6: Simulation setup for RCMV-PWM. 109. Figure 5.7: Simulation setup for H7 inverter with MDPWM. 110. Figure 5.8: Pulse generation for RCMV-PWM. 111. Figure 5.9: Pulse generation for MDPWM. 111. Figure 5.10: Line-to-line output voltage (top) and grid current (bottom) for SVPWM 112 Figure 5.11: Line-to-line output voltage (top) and grid current (bottom) for DPWM 112 Figure 5.12: Line-to-line output voltage (top) and grid current (bottom) for AZPWM 113 Figure 5.13: Line-to-line output voltage (top) and grid current (bottom) for NSPWM 113 Figure 5.14: Line-to-line output voltage (top) and grid current (bottom) for H7 inverter with proposed MDPWM. 114. Figure 5.15: CMV (top) and leakage current (bottom) for SVPWM. 115. Figure 5.16: CMV (top) and leakage current (bottom) for DPWM. 115. Figure 5.17: CMV (top) and leakage current (bottom) for AZPWM. 116. Figure 5.18: CMV (top) and leakage current (bottom) for NSPWM. 116 xiv.

(13) Figure 5.19: CMV (top) and leakage current (bottom) for H7 inverter with proposed MDPWM 117 Figure 5.20: Zoom-in waveforms of CMV (top) and leakage current (bottom) for H7 with proposed MDPWM, showing CMV oscillation during freewheeling period 118 Figure 5.21: Experimental setup. 119. Figure 5.22: Line-to-line voltage (CH1), output current (CH3), and leakage current (CH4) for SVPWM. 121. Figure 5.23: Line-to-line voltage (CH1), output current (CH3), and leakage current (CH4) for DPWM 121 Figure 5.24: Line-to-line voltage (CH1), output current (CH3), and leakage current (CH4) for AZPWM 122 Figure 5.25: Line-to-line voltage (CH1), output current (CH3), and leakage current (CH4) for NSPWM 123 Figure 5.26: Line-to-line voltage (CH1), output current (CH3), and leakage current (CH4) for H7 inverter with proposed MDPWM 124 Figure 5.27: Experimental result of dc-link voltage ripples for various modulation techniques. 125. xv.

(14) List of Tables Table 1.1: Universal single-phase transformerless prototype and parameters. 6. Table 1.2: Universal single-phase transformerless prototype and parameters. 7. Table 3.1: Pulse patterns for various PWM methods. 44. Table 4.1: Parameters for losses simulation. 79. Table 4.2: Parameters of universal inverter. 84. Table 4.3: Performance comparisons for various transformerless topologies. 94. Table 5.1: Vectors combination and corresponding CMV for MDPWM. 97. Table 5.2: Pulse pattern for proposed MDPWM. 98. Table 5.3: Parameters of universal inverter. 119. Table 5.4: Performance comparisons for various PWM. 127. xvi.

(15) LIST OF SYMBOLS AND ABBREVIATIONS Symbols VDC. Direct current supply voltage. VAN, VBN, VCN Load node voltage with respect to the neutral of the dc bus VFP. Freewheeling path voltage. C1, C2. DC bus capacitor. CPV. Stray capacitance. Lf. Filtering inductance. RG. Ground resistance. f. Grid frequency. fs. Switching frequency. Lf. Filter inductor. Ig. Grid current. Vg. Grid voltage. VDM. Differential-mode voltage. VCM. Common-mode voltage. VECM. Equivalent common-mode voltage. IL. Leakage current. m. Modulation Index. CEC. Californian efficiency. Va, Vb, Vc. Original sinusoidal reference signals. Va*, Vb*, Vc* Resultant modulation signals after injecting of zero-sequence signal V0. Zero sequence signal. Vmax. Original sinusoidal reference signals with maximum magnitude. VCE(SAT). Saturation voltage. IC. On-state current xvii.

(16) VF. Diode forward voltage. IF. Freewheeling current. EON, EOFF. Turn-on and turn-off energy losses of the IGBT. VDC_DATASHEET Dc bus voltage in the EON and EOFF characteristic of the datasheet PCON_IGBT. Conduction losses of IGBT. PSW_D. Conduction losses of freewheeling diode. PSW_ON. Turn on losses of IGBT. PSW_OFF. Turn off losses of IGBT. PSW_IGBT. Total switching losses of IGBT. Abbreviations PV. Photovoltaic. PWM. Pulse-Width Modulation. EPWM. Enhanced Pulse-Width Modulation. RCMV-PWM Reduced Common-Mode-Voltage Pulse-Width Modulation SPWM. Sinusoidal Pulse-Width Modulation. SVPWM. Space-Vector Pulse-Width Modulation. DPWM. Discontinuous Pulse-Width Modulation. AZPWM. Active Zero-State Pulse-Width Modulation. NSPWM. Near-State Pulse-Width Modulation. MDPWM. Modified Discontinuous Pulse-Width Modulation. THD. Total Harmonic Distortion. DC. Direct Current. AC. Alternating Current. EMI. Electromagnetic Interference xviii.

(17) MPPT. Maximum Power Point Tracking. CMV. Common-Mode Voltage. IGBT. Insulated Gate Bipolar Transistor. MOSFET. Metal-Oxide Semiconductor Field Effect Transistor. DSP. Digital Signal Processor. NPC. Neutral-Point Clamped. xix.

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