LOOP-BACK TEST MODE

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DEVELOPING TLV320A1C10 V93K DUAL SITES TEST SOLUTION INCLUDING DIGITAL

LOOP-BACK TEST MODE

MOHAMAD NIZAM BIN OTHMAN

UNIVERSITI SAINS MALAYSIA

2019

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DEVELOPING TLV320A1C10 V93K DUAL SITES TEST SOLUTION INCLUDING DIGITAL

LOOP-BACK TEST MODE

by

MOHAMAD NIZAM BIN OTHMAN

Thesis submitted in fulfilment of the requirements for the degree of

Bachelor of Engineering (Electronic Engineering)

June 2019

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ACKNOWLEDGEMENT

The Final Year Project (FYP) that I had with collaboration ADVANTEST was a great chance for learning and professional development. Therefore, I consider myself as a very lucky individual as I was provided with an opportunity to be a part of it. I am also grateful for having a chance to learn new knowledge and experience during my internship and use it to do my FYP that will contribute to this industry.

Bearing in mind previous I am using this opportunity to express my deepest gratitude and special thanks to my supervisor Dr Mohamad Azhar Md Zawawi who in spite of being extraordinarily busy with their duties, took time out to hear, guide and keep me on the correct path and allowing me to carry out my project at their esteemed organization and extending during the FYP

I express my deepest thanks to Mr Harjit Singh for taking part in useful decision & giving necessary advices and guidance and arranged all facilities to make life easier. I choose this moment to acknowledge his/her contribution gratefully.

I perceive as this opportunity as a big milestone in my career development. I will strive to use gained skills and knowledge in the best possible way, and I will finish on my project, in order to attain desired company objectives. Hope to continue cooperation with all of you in the future.

Thank You

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TABLE OF CONTENTS

ACKNOWLEDGEMENT ... ii

TABLE OF CONTENTS ... iii

LIST OF TABLES ... vi

LIST OF FIGURES ... vii

LIST OF ABBREVIATIONS ... xii

LIST OF SYMBOLS ... xiii

ABSTRAK ... ix

ABSTRACT ... x

CHAPTER 1 INTRODUCTION ... 1

1.1 Research Background ... 1

1.2 Problem Statement ... 2

1.3 Objective of Research ... 3

1.4 Scope of Research ... 3

1.5 Thesis Organization ... 4

CHAPTER 2 LITERATURE REVIEW ... 5

2.1 Overview ... 5

2.2 V93000 SOC ATE ... 5

2.3 Classes of V93K ... 6

2.4 TLV320AIC10 (Audio CODEX by Texas Instruments) ... 8

2.5 Smartest software ... 11

2.6 Test setup ... 12

2.7 Comparison between CX1000 and V93K ATE ... 12

2.8 Summary ... 14

CHAPTER 3 METHODOLOGY ... 15

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3.1 Overview ... 15

3.2 Study datasheet/design data TLV320AIC10 (DUT)... 16

3.3 Developing ATE Test Plan ... 16

3.4 Developing Test Program ... 16

3.4.1 Define Pins configuration... 16

3.4.2 Levels Setup ... 19

3.4.3 Timing Setup ... 20

3.4.4 Vectors and Patterns ... 20

3.4.5 Test flow program ... 21

3.4.5.1 Continuity Test ... 23

3.4.5.2 Leakage Test (IIH, IIL) ... 25

3.4.5.3 Functional Test ... 27

3.4.5.4 Dynamic Operating Current Test (AVDD/DVDD) ... 30

3.4.5.5 Reference output voltage Test (VMID) ... 34

3.4.5.6 Frequency Test (SCLK/FS) ... 36

3.4.5.7 ADC Distortion Test ... 42

3.4.5.8 DAC Distortion Test ... 44

3.4.5.9 Additional Test: Digital Loop-Back Test Mode ... 46

3.5 Summary ... 48

CHAPTER 4 RESULT AND DISCUSSION ... 49

4.1 Overview ... 49

4.2 Verify the Test flow ... 49

4.2.1 Continuity Test ... 51

4.2.2 Leakage Test (IIH,IIL) ... 52

4.2.3 Functional Test ... 53

4.2.4 Dynamic Current Test (AVDD/DVDD) ... 55

4.2.5 Reference Voltage Test (VMID) ... 56

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4.2.6 Frequency Test (SCLK/FS) ... 57

4.2.7 ADC Distortion Test ... 59

4.2.8 DAC Distortion Test ... 61

4.2.9 Additional Test: Digital Loop-Back Test Mode ... 64

4.3 Summary ... 66

CHAPTER 5 CONCLUSION AND FUTURE WORK ... 67

5.1 Conclusion ... 67

5.2 Ongoing Issue and Future Improvement... 68

REFERENCES ... 69 APPENDIX A: SOURCE CODE

APPENDIX B: PATTERN/VECTOR APPENDIX C: DATASHEET

APPENDIX D: SCHEMATIC TLV320AIC10

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LIST OF TABLES

Table 2.3.1 The comparison of V93K classes ... 7

Table 2.7.1 The feature and advantage for V93K tester ... 13

Table 2.7.2 The feature and advantage for CX1000 tester ... 13

Table 3.4.1.1 Group pin ... 19

Table 3.4.5.1 Test list ... 21

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LIST OF FIGURES

Figure 1.1.1 Mixed signal testing ... 1

Figure 1.1.2 Dual-site test ... 2

Figure 2.2.1 V93K Tester ... 5

Figure 2.3.1 V93K classes ... 6

Figure 2.4.1 Functional block for TLV320AIC10 ... 8

Figure 2.4.2 The primary serial communication timing ... 10

Figure 2.4.3 Secondary serial communication DIN and DOUT data format ... 10

Figure 2.5.1 Smartest structure ... 11

Figure 2.7.1 CX1000 tester ... 13

Figure 3.1 Flow chart of the project... 15

Figure 3.4.1.1 Define pin configuration for TLV320AIC10 in dual sites ... 18

Figure 3.4.2.1 Equation set ... 19

Figure 3.4.3.1 Wavetable and equation set ... 20

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Figure 3.4.4.1 Pattern for primary serial communication ... 20

Figure 3.4.5.1 Flow chart for test program ... 22

Figure 3.4.5.1.1 Continuity test setup ... 24

Figure 3.4.5.2.1 Leakage test setup ... 26

Figure 3.4.5.3.1 Timing diagram for FS pulse mode (M1M0=00) ... 30

Figure 3.4.5.3.2 Timing sequence of primary and secondary communication ... 30

Figure 3.4.5.4.1 Dynamic operating current test setup ... 33

Figure 3.4.5.5.1 Output DC test setup ... 35

Figure 3.4.5.6.1 Frequency test setup ... 41

Figure 3.4.5.7.1 ADC Test ... 43

Figure 3.4.5.8.1 DAC Test ... 45

Figure 3.4.5.9.1 Digital loopback test ... 47

Figure 4.2.1 Test flow verification ... 49

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Figure 4.2.2 Test flow group... 50

Figure 4.2.3 Execution time for each test ... 50

Figure 4.2.1.1 Continuity test suite ... 51

Figure 4.2.1.2 Continuity test report UI ... 51

Figure 4.2.2.1 Leakage test suite ... 52

Figure 4.2.2.2 Leakage test report UI ... 52

Figure 4.2.3.1 Functional test group ... 53

Figure 4.2.3.2 Functional test report UI ... 53

Figure 4.2.3.3 Timing diagram "funct1" ... 54

Figure 4.2.3.4 Timing diagram "Funct2" ... 54

Figure 4.2.4.1 Dynamic current test suite ... 55

Figure 4.2.4.2 Dynamic current test report UI ... 55

Figure 4.2.5.1 Reference voltage test suite ... 56

Figure 4.2.5.2 VMID report UI ... 56

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Figure 4.2.6.1 Frequency test suite ... 57

Figure 4.2.6.2 Frequency test report UI ... 58

Figure 4.2.7.1 ADC test suite... 59

Figure 4.2.7.2 ADC distortion test report UI ... 59

Figure 4.2.7.3 ADC distortion waveform ... 60

Figure 4.2.7.4 ADC sine wave capture ... 60

Figure 4.2.7.5 ADC shuffle sine wave ... 61

Figure 4.2.8.1 DAC test suite... 61

Figure 4.2.8.2 DAC distortion test report UI ... 62

Figure 4.2.8.3 DAC distortion waveform ... 62

Figure 4.2.8.4 DAC sine wave capture ... 63

Figure 4.2.8.5 DAC shuffled sine wave ... 63

Figure 4.2.9.1 Digital loopback test suite ... 64

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Figure 4.2.9.2 Digital loopback test report UI ... 64

Figure 4.2.9.3 Digital loopback waveform ... 65

Figure 4.2.9.4 DLB sine wave capture ... 65

Figure 4.2.9.5 DLB shuffled sine wave ... 65

Figure 4.2.9.6 Input sine wave from oscilloscope ... 66

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LIST OF ABBREVIATIONS ATE Automated Test Equipment

DUT Device Under Test COT Cost-of-Test

IC Integrated Circuit UPH Unit Per Hour

DSP Digital Signal Processor ADC Analog to Digital Converter DAC Digital to Analog Converter

IP Intellectual Property SOC System On Chip CPU Central Processing Unit VOIP Voice over Internet Protocol

API Application Processing Interface UTM Universal Test Method

TMU Time Measurement Unit AWG Arbitrary Waveform Generator DGT/DGTZ Digitizer

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LIST OF SYMBOLS N Number of sample/data/ frequency divider

FS Sampling frequency

VDD Supply voltage

VIL Maximum low-level input voltage

VIH Minimum high-level input voltage

VOL Maximum low-level output voltage

VOH Minimum high level output voltage

UPU Unit Per Hour

MCLK Master Clock Frequency=8.192MHz

SCLK Slave Clock Frequency

IIL Maximum low-level input current

IIH Minimum high-level input current

VMID Reference Output Voltage

SNR Signal to noise ratio

THD Total harmonic distortion

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DEVELOPING TLV320A1C10 V93K DUAL SITES TEST SOLUTION INCLUDING DIGITAL LOOP-BACK TEST MODE

ABSTRAK

Uji kaji adalah langkah yang terakhir dalam process pembuatan terutamanya ia digunakan dalam industri semikonduktor yang memproses litar bersepadu (IC). Kini, litar bersepadu (IC) mendapat permintaan yang tinggi dan ia sangat berguna dalam banyak aplikasi seperti computer, kenderaan, peralatan industri dan lain-lain. Oleh itu ujian IC sangat rumit dan perlu melaksanakan banyak ujian untuk memastikan prestasi mematuhi spesifikasi dan meningkatkan kos produk. Projek ini merujuk tentang bagaimana untuk uji IC dalam jalan alternatif untuk memberi faedah kepada industri semikonduktor kini. Metodologi ini bermula dengan mengkaji dan memahami lembaran data untuk peranti dibawah ujian (DUT) dan kemudian membuat plan ujian sebagai garis panduan. Ia sangat penting kerana ia memudahkan untuk melaksanakan program ujian untuk peranti ini sebagai ujian. Project ini, penguji V93K digunakan untuk uji DUT selepas ia diletakkan atas penguji dan perisian V93K digunakan sebagai platform untuk membina program ujian dan berinteraksi antara penguna dan penguji untuk menguji DUT. Ujian tambahan yang terlibat dalam program ujian adalah mod ujian digital ulang-alik. Selepas semua ujian selesaikan masalah, keputusan sepatutnya mendapat semua lulus. Pelaksanaan ujian selari bagi 100ms dengan 20ms dimana gagal dalam kadar 20% akan beri kesan yang negative dalam masa ujian pengeluaran dan menyediakan masa ini 20ms untuk urutan program yang pertama. Secara general, masa ujian bagi teras IP yang sangat lama sepatutnya tidak kurang 50% bagi keseluruhan masa ujian. Dengan keputusan ini, ia disimpulkan semua ujian pada DUT akan lulus dengan membezakan keputusan sebenar melalui program ujian dengan lembaran data bagi DUT. Ia bermaksud keputusan daripda ujian program (simulasi) adalah hampir sama dengan keputusan dari lembaran data DUT. Ia boleh mencapai meningkatan dengan mengunakan metodologi yang dicadangkan.

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DEVELOPING TLV320A1C10 V93K DUAL SITES TEST SOLUTION INCLUDING DIGITAL LOOP-BACK TEST MODE

ABSTRACT

Testing is the final step in manufacturing process especially it used in semiconductor industry that process the integrated circuit (IC). Nowadays, IC is more demanding and it is useful in any application such as computer, vehicle, appliance in industrial and many more. So that, testing the IC is getting complicated and need to do lot of tests on IC to ensure the performance comply into specification and improve product cost. For this project is about on how to test the integrated circuit (IC) in alternative ways to bring benefits to semiconductor industry today. The improved methodology is started studying and understand the datasheet for DUT and then create the test plan as a guideline. It is important because it would make easier to do the test program for this device for testing. In this project, the V93K tester is used to test the DUT after placing on it and V93K software is used as a platform for developing the test program and interface between user and tester for testing the DUT. The additional test is involved in test program is digital loop-back test mode. After all tests are debugged, the result should get all pass in dual sites. The parallel test execution of a 100ms with a 20ms which fails at rate of 20% will effect negatively the production test time and provide that the 20ms was the first to be test in sequence program. In general, the test time of the slowest IP core should be less than 50% of the overall test time. With these results, it is deduced that all tests on DUT will be passed when comparing the actual results from test program with the DUT datasheet. It means the results from test program (simulation) are almost same with the results from DUT datasheet. It can be achieving the improvement by using proposed methodology.

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CHAPTER 1 INTRODUCTION 1.1 Research Background

Semiconductor industry is one of the most active industries that involve in the process of semiconductor device especially integrated circuit (IC). Today, testing is useful in manufacturing process and it is the final stage before assembly to produce final product for example phone, washing machine and many more. The purpose is to screen out manufacturing defeat example fab process and assembly process. Besides, another aim is to meet AC/DC specification in datasheet and separate devices base on speed. The aim of testing is improve manufacturing process for better product quality and reliability.

Mixed signal testing is involved in analog and digital operation. It usually uses to test the IC which has DAC and ADC operation or mixed signal IC. There are certainly of issues that will make testing the mixed signal testing mixed signal IC difficult and costly. It also leads low-cost testing for mixed signal testing on DUT.[1]

Three basic categories are test development time, performance and production cost.

One of the most time consuming task during the test development phase is design of the DUT board where IC is inserted and run on mixed signal tester.[2] Figure 1.1.1:

shows mixed signal testing diagram.

Figure 1.1.1 Mixed signal testing

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Testing the IC involve in single-site and dual-site. Single-site is test the DUT in one site. The test time taken for single-site is 1.000sec. So that, the COT for this site 1.00. The benefit testing in dual-site or multi sites can reduce the cost-of-test (COT) at the DUT and final test. Dual-site test is operation or run the test the DUT in dual-site in a time when placing the two DUT on DUT board with two sites. So, this test can reduce IC testing time and also reduce IC cost. Dual-site testing required another set of tester resources to test the second DUT. The Dual-site test time is 1.025sec. COT is cost per hour ($/hour) required per unit per hour (unit/hour) or the cost to test the DUT in an hour. The COT for dual-site test is 0.78. Another parameter needs to consider for testing DUT is Unit per hour (UPH) and Test time per hour.

UPH is number of device in test cell per hour. Test time per hour is test time of each device including the index time of handler. The multi-site efficiency for dual-site test is more than 97%.[3] Figure 1.1.2 shows the dual-site test.

.

Figure 1.1.2 Dual-site test 1.2 Problem Statement

As the world now leading the new technology, the recent technology advance is semiconductor IC testing technology which is ATE for testing the sensory system, low power IC management, DSP audio IC and everything. The demand on the semiconductor IC testing technology is increasing, but it was not efficient enough. In this part, it will state several obstacles regarding the issue.

First of all, IC has small size which has a typical chip areas range a few millimeter square. So that, it is too difficult to measure or test using common instrument such as multimeter, voltmeter and ammeter directly to IC. It needs to be

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setup manually before test the IC. Consequently, it takes a long testing time to test the IC. It is because there have many IC need to be tested before assembly to product. As we know, IC needs to be performed many tests such as digital/analog test, mixed signal test and RF test to ensure that IC is not failure especially architecture, connection and functional.

Besides, IC has the complexity circuit because it has a million or more transistors in IC. So that, IC needs to be measured to ensure that each of the transistors inside the IC are working properly. Therefore, it is difficult to measure the IC using common instruments. Sometimes, IC need to measure accurately in order to ensure IC can perform the operation properly and does not have defeat.

Next, the main problem in IC testing is does not include digital loop back in test list. It is because this additional test is important to increase the level of parallelism in mixed signal test without suffering from the fault masking problem.[4]

1.3 Objective of Research

The purpose of this project is to develop the test program for TLV320AIC10 as a DUT and some additional test is digital loop-back test mode by using V93K in dual sites. For the final aim, the objective of this thesis is to verify the test program development for TLV320AIC10 and some additional test is digital loop-back test mode. The objective:

i. To develop the TLV320AIC10 V93K dual sites test solution using V93K Smartest software.

ii. To implement the V93K test solution for TLV320AIC10 in dual sites by including a digital loop-back test mode.

1.4 Scope of Research

In this final year project, it will be focused on developing the test program on DUT using ATE. This project also focuses on Digital, Analog, Mixed Signal Testing and some additional test which is Digital Loop-back Test Mode. The Test plan needs to be created by referring the TLV320AIC10 datasheet as DUT and then develop the Test program for this DUT before debugging it to make sure all tests are passed. The Test program will be developed by using Smartest software.

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This project will undergo three different stages for test program development.

First, create the Test program for all tests setup based on test plan guide. Then, each of tests setup as known as tests suite need to debug to make all tests pass. Next, the Test program will be introduced as future work.

1.5 Thesis Organization

This thesis consists 5 major chapters. In chapter 1, the introduction is described on the general review of the whole project. In chapter 2, Literature review will explain the related research history, useful information, theory and experimental and the topic about this title FYP. The project focuses on Testing on DUT, ATE and the fundamental of semiconductor test production.

In chapter 3, Methodology will apply the systematic and theoretical analysis of the flow method in this project. This chapter also will elaborate the process of work from the start until the end including the developing the test program, debugging, testing and measuring that have been conducted from experiment.

In chapter 4, Result and Discussion will include the results and observation that can be discussed. In chapter 5, Conclusion and future work is the last chapter that will summarize this whole project and give the suggestion about future improvement.

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CHAPTER 2 LITERATURE REVIEW 2.1 Overview

This chapter will describe the element or scope involved in Final Year Project (FYP). It can be said that test development is demanding and still to grow in popularity while having an integral part for both personal and business communication. Besides, the Automated Test Equipment (ATE) there are various of thing can be made. In this chapter it also describes a test development, test setups, DUT and the contribution of V93K SOC ATE.

2.2 V93000 SOC ATE

Figure 2.2.1 V93K Tester

In figure 2.2.1 shows the Automated Test Equipment (ATE) that used in this project is V93000 ATE. ATE is a system that is composed of test instruments capable of applying response and making accurate measurement under the control of CPU. It is widely used in semiconductor industry to perform measurement and calculation of test result during manufacturing and maintenance.[5]ATE can test a wide range of devices and system, from simple components like resistor, capacitor and inductor to IC, printed circuit board (PCB), and complex, completely assembled electronic systems. ATE is needed for testing the devices before installing in the application to reduce defect from product, process and service.[6]Besides, it reduces the manufacturing cost.

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In V93K SoC/Smart scale tester have full suite of capabilities which are direct current (dc), digital, high speed digital, analog and RF. There have few parts of V93K tester which are emergency stop, On/standby switches, support rack, manipulator, DUT board and Testhead..

Test head contain all instruments cards which are power supply, signal source and measure instruments. It contains pogo cables that used for connecting wires between instrument cards and DUT interface or interface board. DUT interface helps to connect the signal from the instrument cards to DUT. Next, manipulator help to dock the test head to the handler or prober setup. Support rack provides AC/DC power conversion and power distribution for test head. DUT board is used to place DUT on test head for testing. DUT board have pogo pin interconnect are commonly used for connecting Automatic Test Equipment (ATE) measurement channel to the device under test (DUT).[7]

2.3 Classes of V93K

In this section, there have 4 types of classes for V93K tester and its comparison. Figure 2.3.1 shows the V93K classes.

Figure 2.3.1 V93K classes

The similarity is all classes V93K are compatible. The difference between its classes is the size of the testhead which are number of card cags, pin scale 1600

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channel, pin scale 400/9G channel, pin scale 800/3600 channel. Table 2.3.1 shows the comparison V93K classes.

Table 2.3.1 The comparison of V93K classes Available

resources

A-class Test Head

C-class Test Head

S-class Test Head

L-class Test Head Number of card

cages

1 2 4 8

Pin scale 1600 channel

1024 2048 4096 4096

Pin scale 400/9G channel

512 1024 2048 2048

Pin scale 800/3600 channel

256 512 1024 2048

In this project, A-class test head V93K tester is used. It equip 1 card cages.

These modules have Pins scale 1600s which is digital channel cards, MS-DPS means multisite device power supply, MBAV8+ for analog channel cards and port scale RF which is RF cards.

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2.4 TLV320AIC10 (Audio CODEX by Texas Instruments) [8]

Figure 2.4.1 Functional block for TLV320AIC10

The TLV320AIC10 is a IC component as device under test (DUT) by using V93000 tester to develop V93000 test solution for its DUT in dual sites by including a digital loop-back test mode. In the order word, TLV320AIC10 is an audio CODEC device that used as DSP IC interfacing for audio signal I/O processing. This device fulfilled for a wide range of interfacing communication in DSP, continuous/analog signal bandwidth and analog level. This DUT contain signal resolution with high resolution from Analog-to-Digital (A/D) and Digital-to-Analog (D/A) conversion by using oversampling sigma-delta technology.

This device has 2-to-1 MUX input with built-in antialiasing filter and amplification for general-purpose application such as telephone hybrid interface, electret microphone preamp and etc. Both IN and AUX input can accept normal continuous signal. It consists of a pair of 16-bit synchronous serial conversion paths for each direction. It consist various type of filters which are an interpolation filter at before DAC and a decimation filter at after the ADC. Offer flexibility and power savings is bypassed by FIR Filter. The other overhead functions consist on-chip include timing such as programmable sample rate, continuous data transfer and FIR bypass and control such as programmable-gain amplifier, communication protocol and

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etc. The sigma-delta architecture produces high-resolution ADC and DAC at low system cost.

For TLV320AIC10 design enhance communication in DSP. The continuous data transfer obviously support TI’s DSP auto-buffering (ABU) to reduce interrupt service overhead. Besides, automatic cascading detection (ACD) provide cascade programming simple and supports a cascade operation for one master until up to seven slaves. The direct-configuration mode for host interface uses a single-wire serial port connect directly to program interval register without interference from the data conversion serial port or resetting the entire device. The event monitor mode allows the DSP to monitor external events example phone off-hook ring detection. This device will convert data at 8 KSPS sampling rate that consume 39mW at lower-power mode.

The programmable functions for this device configure through a serial interface that can be not comparable interfaced to any DSP that accepts 4-wire serial communications such as the TMS320Cxx. The options consist software reset, device power-down, separate control for ADC and DAC turnoff, communication protocol, signal-sampling rate, gain control and system-test modes. The application for this device is particularly suitable in hand-free car kits, VOIP, cable modem, speech and telephony area including low-bit rate, high-quality compression, speech enhancement, recognition and synthesis. For low-group delay characteristic makes suitable for a single or multichannel active-control applications. This device is characterized for commercial operation from 0ºC to 70ºC and industrial operation from -40ºC to 85ºC.

This Audio CODEX performs serial communication for signal and register data toward DOUT and DIN pins. It performs 2 window of data transfer which are primary and secondary serial communication. For primary serial communication used to transmit and receive conversion signal data. Secondary serial communication used to read and write in 16-bit words to the register to control the device configuration.

Figure 2.4.2 and figure 2.4.3 shows the primary serial communication timing and secondary serial communication DIN and DOUT data format respectively.

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Figure 2.4.2 The primary serial communication timing

Figure 2.4.3 Secondary serial communication DIN and DOUT data format Operating frequency for this device, sampling frequency is represented by frequency for primary serial communication that derived from master clock (MCLK) with the equation,

sampling(conversion) frequency, Fs = MCLK

256xN, N = 1,2, … ,32 (2.4.1)

The inverse of sampling frequency is time between the falling edges of two successive primary frame-sync signals. This time is conversion period. Example, to set conversion rate to 8kHz, MCLK=256xNx8000. Note that, the value of N is defined in control register 2 and its power up value is 32.

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SCLK = 256Fs =MCLK

N , N = 1,2, … ,32 (2.4.2)

When the device is configured as master mode, M_S pins must select HIGH (M_S pin=1), so that SCLK is generated by 256 x Fs. It can be simplified by equation 2.4.2.

2.5 Smartest software

Smartest is software to develop the test program and also as a platform to check the DUT pass/fail result. This software provided ATE vendor the ability to fast the response to market that needs good quality product in a short time.[9] Smartest consist 2 mode which are offline mode and online mode. For offline mode, the workstation or user is not interface with tester while online mode will be interfacing between workstation and tester. This software has their mode because limiting the tester in industry. Figure 2.5.1 shows the Smartest structure.

Figure 2.5.1 Smartest structure

Smartest also can develop, debug and execute the test program. It supplies a variety of customized functions that use C++ programming language for programming operation to do some purpose which are measure the output signal from a test device, retrieve and analyze the measure data and judge the calculated result as pass/fail. Test method API use to customize functions using programming. Starting develop the test program, create the global setup which are define pin configuration, setup level and timing and create pattern. Then, create the test suite for each test using test method program in test flow editor. Select desired test program and primaries. When the test flow is executed, all setup filled are specified in test suite as primary setting in the test flow editor will be automatically download to the tester hardware to test the DUT.

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Test setup that developed from Smartest is executed to the V93K tester for testing and then all the results are shown in Smartest software in report UI or datalog. Besides, it also shows the test is pass/fail.

2.6 Test setup

Test setups that involve in this project have 20 test setups which are continuity test input leakage test, functional test, supply current test, VMID output voltage test, frequency test, DAC linearity and distortion test and ADC linearity and distortion test.

All 20 test setups can be simplified by creating universal test method (UTM). The test setup simplify to 8 test suits.

Some additional test is digital loop-back test mode. Digital loop back testing a modem data ADC/DAC channel to use for in circuit system level test. Digital loop- back routes the ADC output to DAC input on the device. Digital loop-back is enabled by writing 10 to D6 and D7 in control register 3 (D6=0, D7=1). Control register 3 is enabled when register address at D11 is OFF and D10 and D9 are ON (D11=0, D10=1, D9=1). In this test, the analog input data is transmitted to analog input pin which is INP pin and then loop-back operation when digital loop-back is enabled by short the DIN and DOUT pins. So that, the analog input data convert to digital output data by DAC and then loop-back digital output data become digital input data. Then convert back from digital input data to analog output data by ADC and it measure by using digitizer that connect to analog output pin which is OUTP pin. The purpose of loop-back test is to synthesize the desired stimulus or responses.[10]So that, the digitizer capture the signal at OUTP pin. The result analog signal input (INP) is same with analog signal output OUTP.

2.7 Comparison between CX1000 and V93K ATE

In this section, the V93K tester is needed to be compared and described with another tester which is CX1000. The feature and advantage for V93K tester is showed in table 2.7.1 and the feature and advantage for CX1000 tester showed in table 2.7.2.

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Table 2.7.1 The feature and advantage for V93K tester

Feature Advantage

Scalable support of digital, mixed signal and RF device

Ideal for wireless, maximum test resources utilization for greatest return on capital investment

Test head in direct contact with probe card High performance signal integrity fur functional test

Multi-site (up to32 site) capability High parallelism and throughput to lower cost of test

Contact force up to 300kg with superior planarity

Excellent contact quality for large die and high pin count devices

Table 2.7.2 The feature and advantage for CX1000 tester

Feature Advantage

FUNC Connector connect between Universal board and tester

High flexibility to cloud testing station

Relay circuit, power supply and instruments placed near to universal board

Wide Universal area of board

Two types of relay are conventional mechanical relay for low contact resistance and PhotoMOS relay for low drive current

Flexible relay selection and quick connection for preprinted relay on board

Figure 2.7.1 CX1000 tester

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Figure 2.7.1 shows the CX1000 tester that used for testing the devices. There have a few similarity between CX1000 and V93K tester because both are automatic test equipment (ATE) that offer the ability to verify a product functionality and provide pass/fail result. Beside, Both of them can automated troubleshooting, reduce troubleshooting time, faster fault isolation time and more accurate isolation resulting in less rework.[11]

In software part, Both testers uses Graphical User Interface (GUI) tools to enable debugging at different abstraction levels which are test scenario level, pattern cycle and timing and wave tools.[12] The different between V93K and CX1000 are classes. V93K have 4 classes which are V93000-A, V93000-C, V93000-S and V93000-L whereas CX1000 have 3 classes, CX1000P, CX1000D and CX1000D S2- LINK. Besides, software tool uses as platform for V93K is SmarTest software whereas CX1000 software tool is CloudTesting station. But both software tools use to setup the test for DUT and as part of the test development process.

2.8 Summary

This chapter described the introduction of ATE and architecture for V93K tester that use in semiconductor industry today and also comparison between V93K tester classes, V93000-A, V93000-C, V93000-S and V93000-L. Besides, TLV320AIC10 as DUT for this project is explained. This chapter also explain the Smartest software and its used. Lastly, the CX1000 and V93K ATE are compared and described.

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CHAPTER 3 METHODOLOGY 3.1 Overview

This chapter will explain all processes or the method involved in this project.

From setup the DUT with is TLV320AIC10 on V93000 based on schematic circuit until create the test program and debugging the test program. In this chapter will be discussed the methodology for this project and related current topic for understanding and get some knowledge and idea on how the project is conducted. The first step to start this project is study TLV320AIC10 datasheet, extract the parameter from datasheet, perform what type of testing is used and get other information on related topic purpose.

Next, develop ATE test plan for this TLV320AIC10. The next step is developed the Test program with required test list and test plan as a guide. The test program is developed using Smartest software. Then, the test program is needed to debug to pass all tests. The result will be shown in data log. The flow chart for this project is shown in figure 3.1.

Figure 3.1 Flow chart of the project

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3.2 Study datasheet/design data TLV320AIC10 (DUT)

As the test development research, the first step is study the datasheet, test plan and design data about device that will be tested on tester. So that, the device that needed to be test on V93K is TLV320AIC10. DUT had been explained in chapter 2.

3.3 Developing ATE Test Plan

After understanding the datasheet, next step is developing the ATE test plan to guide on how to setup any tests on DUT. Besides, it suitable used as presentation slide because it easy to understand on how the test is setup. There consists 3 type need to have in test plan which are test information, test condition and test procedure.

Example test plan is shown as section 3.4.

3.4 Developing Test Program

Test program is developed by using Smartest software in offline mode. In test program need to define pins configuration, level and timing setup, create pattern and develop test flow. Then, this test program is debugging before run the test flow to ensure the test is passed and it show the result in Report UI or data-log.

3.4.1 Define Pins configuration

First of all, define the pin in order to define the connections between device pin and tester resources in dual sites. So that, figure 3.4.1.1 below shows the definition pin configuration for TLV320AIC10 in dual site. (Refer from appendix D)

Digital Pin

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Analog pin

DPS pin

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Utility pin

Trigger pin

Figure 3.4.1.1 Define pin configuration for TLV320AIC10 in dual sites

After defining the pins, next step is defining pin group and it show in table 3.4.1.1 the pin group. There have 5 pin group are created.

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Table 3.4.1.1 Group pin

continuity M0,M1,PWRDN/,RESET,DOUT,DIN,SCLK,MCLK,FSD,FS,FLAG ,FC,DCSI,M_S/,VMID

i_pin M0,M1, PWRDN/, DIN, FC,DCSI,M_S/

INPUT_pin M0,M1, PWRDN/,RESET, DIN, FC,DCSI,M_S/

IO_pin SCLK,FS

OUTPUT_pin FSD,FLAG,VMID Ports(DSM) DIN

3.4.2 Levels Setup

Level setup is the step where considering the DC electrical characteristics of a DUT versus the pin electronic of the V93K system. Level is setup by creating the equation set and the create spec that shows in figure 3.4.2.1. For this project, no termination is used.

Figure 3.4.2.1 Equation set

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3.4.3 Timing Setup

Timing setup is useful to setup the waveforms or signals. To setup the timing is create the equation set and wavetable. Then, create spec that shows in figure 3.4.3.1.

Figure 3.4.3.1 Wavetable and equation set 3.4.4 Vectors and Patterns

Vector setup is determining the sequence of waveforms sent to the DUT during test execution. Figure 3.4.4.1 shows how to create the pattern for primary serial communication. (Refer from appendix B)

Figure 3.4.4.1 Pattern for primary serial communication

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3.4.5 Test flow program

In this section, the test flow for this TLV320AIC10 is created to setup all 20 test suite for common tests based on test list that shown in table 3.5 and including 1 test suite for additional test which is digital loop back test mode.

Table 3.4.5.1 Test list

Last test is some additional test which is digital loop back test mode that will explain at section 3.4.5.9. Figure 3.4.5.1 below shows that the flow chart for developing test program for TLV320AIC10.

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Figure 3.4.5.1 Flow chart for test program

Based on this flow chart, test program is started by creating the device (DUT) which is TLV320AIC10. The tests are setup by selecting test method and insert the limits for each test. Then, this test is executed to check whether this test pass or fail. If the test is failed, test need to debug until pass after executing. For the test is passed, the process is repeated for the next test.

After all tests are passed, the results are collected in report UI, timing diagram and signal analyzer for analysis and comparing the actual result which datasheet.

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3.4.5.1 Continuity Test Test Information

Test Conditions

DUT configurations and pins to resource connections

Default connections

AVDD, DVDD 0V

Forced Pins All digital pins

Measured Pins All digital pins

Forced signal level -100uA

Instrument used to Force Digital Channel PPMU

Instrument used to measure Digital Channel PPMU

Pattern -

Vector rate -

Digital levels -

Datasheet Reference

-

Test Number 1

Test Name Continuity

Test Limits -0.2V <= X <= -0.6V Fail Bin 2 ( SW ) 2 ( HW )

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Test Procedures

1. Configure and connect DUT to tester resources: Default

2. Set AVDD, DVDD = 0V (current compliance setting depends on the expected total loading from DUT)

3. Set PPMU for all digital pins to -100uA 4. Wait for 4ms settling time

5. Measure PPMU Voltage for all digital pins

6. Verify this test pass/fail and log continuity(neg) results in mV

Figure 3.4.5.1.1 Continuity test setup

The purpose continuity test is to check the chip bonding and connection to test fixture, check protection circuit in the DUT such as clamp diode and check for short- circuits that causing current leak. Since only clamp diode is present in this DUT, the test is executed in single polarity mode using digital channel PPMU for all digital pin by force -100uA out of device pin to PPMU and measuring voltage between pin and ground. The voltage is detected in forward bias voltage for clamp diode. The result voltage will be equal to voltage rail PPMU (either positive or negative extremely) when there is no internal connection between pin and ground. It is because PPMU cannot force or sink the current specified. If the result there is no voltage, the short circuit has been detected.

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3.4.5.2 Leakage Test (IIH, IIL) Test Information

Test Conditions

Default connections

AVDD, DVDD 5V

Forced Pins DIN, FC, M0, M1, MCLK pins

Measured Pins DIN, FC, M0, M1, MCLK pins

Forced signal level Leakage Low : 0.0V (IIL)

Leakage High: 5.0V (IIH)

Pattern Func_leak

Vector rate 8.192 MHz

Digital levels VIL = 0V VIH = 5V

VOL = 2.4V VOH = 2.6V Datasheet

Reference

Table 4.3.1

Test Number 2

Test Name Leakage

Test Limits -1uA <= X <= 1uA Fail Bin 3 ( SW ) 3 ( HW )

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Test Procedures

3. Precondition DUT with pattern “Func_leak” to set input pin to high impedance 4. Set PPMU for “DIN, FC, M0, M1, MCLK pins” group to 0.0V

5. Wait for 3ms settling time

6. Measure PPMU current(IIL) for “DIN, FC, M0, M1, MCLK” pins 7. Set PPMU for “DIN, FC, M0, M1, MCLK pins” group to 5.0V 8. Wait for 3ms settling time

9. Measure PPMU current(IIH) for “DIN, FC, M0, M1, MCLK ” pins

10. Verify this test pass/fail and Log Leakage Low and Leakage High results in uA

Figure 3.4.5.2.1 Leakage test setup

Leakage test is to detect current flow into input pin during forcing particular voltage which are force HIGH and force LOW when device in active or ON condition.

An ideal Input pin no current flow and have infinite impedance. But in actual application, there will have small current flow because of very higher impedance. So that, all input pins need to be set to high impedance state before measuring. This can be done by executing the function pattern that set the DUT into POWER DOWN mode. All test pins is measured in parallel at same time.

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3.4.5.3 Functional Test Primary serial communication Test Information

Test Conditions

Default connections

AVDD, DVDD 5V

Forced Pins -

Measured Pins SCLK,FS

Forced signal level -

Instrument used to measure -

Pattern Funct1

Vector rate 8.192MHz

Reference

-

Test Number 3

Test Name Functional

Test Limits -

Fail Bin 4 ( SW ) 4 ( HW )

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Test Procedures

3. Run pattern “funct1”

4. Return Pass/Fail results

Secondary serial communication Test Information

Test Conditions

Default connections

AVDD, DVDD 5V

Forced Pins -

Measured Pins SCLK,FS,DIN,DOUT

Datasheet Reference

-

Test Number 4

Test Name RdWr_Functional

Test Limits -

Fail Bin 5 ( SW ) 5 ( HW )

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Pattern Funct2

VOL = 2.4V VOH = 2.6V

Test Procedures

4. Return Pass/Fail results

Functional test is a test to verify the true table of the device and return a pass/fail result. The functional test will focus on primary and secondary serial communication.

Based on datasheet, the frequency divider, N=32 (default) which means 32 MCLKs will produce 1 SCLK. The number of SCLKs between FS primary and FS secondary is 128. FS secondary not appear and SCLKs number between FS primary is 256 when secondary communication is disabled. The data are written at DIN or read at DOUT on first 16 SCLKs after FS signal.

Both functional patterns for the device is set to master mode (M_S pin=1) and FS pulse mode (M1=0, M0=0). Device is RESET at the starting of the pattern to restore the register to default value and also to sync pattern to SCLK and FS.

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Figure 3.4.5.3.1 Timing diagram for FS pulse mode (M1M0=00)

Figure 3.4.5.3.2 Timing sequence of primary and secondary communication

3.4.5.4 Dynamic Operating Current Test (AVDD/DVDD) AVDD

Test Information

Datasheet Reference

Table 4.3.10.2

Test Number 5

Test Name AVDD

Test Limits 5mA <= X <= 20mA Fail Bin 6 ( SW ) 6 ( HW )

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Test Conditions

Default connections

AVDD, DVDD 5V

Forced Pins AVDD

Measured Pins AVDD

Forced signal level 0V

Instrument used to Force DPS Power Supply

Pattern Funct1

VOL = 2.4V VOH = 2.6V

Test Procedures

2. Set AVDD = 5V (current compliance setting depends on the expected total loading from DUT)

3. Measure DPS current at pin AVDD during pattern “Funct1” run.

4. Verify this test pass/fail and log DPSIDD results in mA

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DVDD

Test Information

Test Conditions

Default connections

AVDD, DVDD 5V

Forced Pins DVDD

Measured Pins DVDD

Forced signal level 0V

Instrument used to Force DPS Power Supply

Pattern Funct1

Reference

Table 4.3.10.2

Test Number 6

Test Name DVDD

Test Limits 0.1mA <= X <= 5mA Fail Bin 7 ( SW ) 7 ( HW )

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Test Procedures

2. Set DVDD = 5V (current compliance setting depends on the expected total loading from DUT)

3. Measure DPS current at pin DVDD during pattern “Funct1” run 4. Verify this test pass/fail and log DPSIDD results in mA

Figure 3.4.5.4.1 Dynamic operating current test setup

Dynamic operating current (IDD) test is a test measuring the supply current when the device in full operation mode. It means the supplied current is measure when the pattern is executed. The purpose doing this test to check output maximum current consumed when in full function, segregate out the device that potential have reliability issue, checking common manufacturing fault which can easily detect check for short- circuit that causing current leak.

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3.4.5.5 Reference output voltage Test (VMID) Test Information

Test Conditions

Default connections

AVDD, DVDD 5V

Forced Pins -

Measured Pins VMID

Forced signal level -1mA

Pattern Funct1

Reference

Table 1.5

Test Number 7

Test Name VMID

Test Limits 2.45V <= X <= 2.55V Fail Bin 8 ( SW ) 8 ( HW )

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Test Procedures

3. Close relay K1 to connect PPMU with measure pin 4. Run pattern “funt1”

5. Set PPMU for “VMID” pin to -1mA 6. Wait for 3ms settling time

7. Measure PPMU voltage for “VMID” pin 8. Open relay K1

9. Log VMID results in V 10. Wait for 3ms settling time

11. Measure PPMU voltage for “Measured” group 12. Verify this test pass/fail and log VMID results in V

Figure 3.4.5.5.1 Output DC test setup

Output DC test is a test measure the dc output voltage of the DUT under specific current load conditions. VMID is always output AVDD/2 and stable of all time as it called as reference voltage output for external MIC input.

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3.4.5.6 Frequency Test (SCLK/FS) N=32(default)

Test Information

Test Conditions

Default connections

AVDD, DVDD 5V

Forced Pins -

Measured Pins SCLK

Instrument used to Force -

Instrument used to measure Time Measurement Unit (TMU)

Pattern Funct1

Reference

-

Test Number 8

Test Name SCLK_N_32

Test Limits 255.9kHz<=X<=256.1kHz Fail Bin 9 ( SW ) 9 ( HW )

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Test Procedures

2. Set AVDD DVDD = 5V (current compliance setting depends on the expected total loading from DUT)

4. Measure frequency between rising edges and search for pass/fail transition, retrieve last Pass result

5. Log SCLK results in MHz

N=32(default) Test Information

Test Conditions

Default connections

VCC 5V

Forced Pins -

Measured Pins FS

Datasheet Reference

-

Test Number 9

Test Name FS_N_32

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Pattern Funct1

VOL = 2.4V VOH = 2.6V

Test Procedures

5. Log FS results in MHz

N=4

Test Information

Datasheet Reference

-

Test Number 10

Test Name SCLK_N_4

Test Limits 2.04799MHz<=X<=2.04801MHz

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Test Conditions

Default connections

VCC (AVDD/DVDD) 5V

Forced Pins -

Measured Pins SCLK

Pattern Funct2

VOL = 2.4V VOH = 2.6V

Test Procedures

5. Log SCLK results in MHz

Fail Bin 11 ( SW ) 11 ( HW )

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N=4

Test Information

Test Conditions

Default connections

VCC 5V

Forced Pins -

Measured Pins FS

Pattern Funct2

Reference

-

Test Number 11

Test Name FS_N_4

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Test Procedures

5. Log FS results in MHz

Figure 3.4.5.6.1 Frequency test setup

Frequency test is to test the frequency or period of signal for SCLK and FS pins with time measurement unit (TMU). In this test, the SCLK and FS frequency are measured when the frequency divider, N=32(default) and N=4. Frequency divider, N=4 is enabled by control register 2 which is written, D11=0, D10=1, D9=0 and then D2=1 to select N=4. Frequency test is started by executing arming waveforms in a pattern. The purpose is to activate the TMU measurement for measuring the SCLK and FS frequency. “ARM” keyword is written in patterns which are “Funct1” and

“Funct2”.

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3.4.5.7 ADC Distortion Test Test Information

Test Conditions

Default connections

DVDD, AVDD 5V

Forced Pins INP

Measured Pins DOUT

Forced signal level Sine signal, 2V to 3V, 2048 points, 7 cycles, 180-degree phase shifted Instrument used to Force Arbitrary Waveform Generator

(AWG)

Pattern adc

Datasheet Reference

Table 4.3.3

Test Number 12

Test Name ADC_Test

Test Limits Signal-to-noise ratio (SNR): 75dB<=X<=100dB

Total Harmonic Distortion (THD): -120dB<=X<=-90dB 2nd Harmonic: -120dB<=X<=-90dB

3rd Harmonic: -120dB<=X<=-90dB Fail Bin 13 ( SW ) 13 ( HW )

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VOL = 2.4V VOH = 2.6V

Analog Settings Input signal frequency: 1kHz

Sampling frequency: 64 kHz

Test Procedures

1. Configure and connect DUT to tester resources: Default 2. Set DVDD, AVDD = 5V

3. Input sine signal through AWG, trigger one vector before the ramp signal 4. Capture DOUT signal through PPMU

5. Fourier transform the signal into frequency domain

6. Calculate Signal-to-Noise Ratio (SNR), Total Harmonic Distortion (THD), 2nd and 3rd Harmonic.

7. Log waveform in signal analyzer and verify pass/fail

Figure 3.4.5.7.1 ADC Test

ADC distortion test needed to be tested by setup the waveform generator example Arbitrary waveform generator (AWG) to analog input (INP pin) and sine wave is sourced. The waveform sends out from ADC output is captured by digital pin (DOUT) after analog to digital conversion. The AWG triggered by a digital pin. So that, the generated signal and generated capture needs synchronization.

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3.4.5.8 DAC Distortion Test Test Information

Test Conditions

Default connections

DVDD, AVDD 5V

Forced Pins DIN

Measured Pins OUTP

Forced signal level Discrete sine signal, 0x00 to 0xFF, 7cycles, 2048 points

Instrument used to Force Digital Channel

Instrument used to measure Digitizer

Pattern dac

Datasheet Reference

Table 4.3.6

Test Number 13

Test Name DAC_Test

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Digital levels VIL = 0V VIH = 5V VOL = 2.4V VOH = 2.6V

Sampling frequency: 32kHz

Test Procedures

3. Run pattern “dac”, trigger digitizer one vector before the sine signal 4. Capture OUTP signal through digitizer

6. Calculate Signal-to-Noise, Total Harmonic Distortion (THD), 2nd and 3rd Harmonic.

Figure 3.4.5.8.1 DAC Test

DAC distortion should to be tested by setup digital source to DIN pin and digitizer is connected to OUTP pin. It is because sine waves in continuous signal need to convert to discrete data sine wave by download to vector variable. This setup is called digital setup memory (DSM). Then, discrete sine wave as input signals send to DUT. After DAC conversion, output signal in analog waveform captured by digitizer to display the results when digitizer is triggered.

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3.4.5.9 Additional Test: Digital Loop-Back Test Mode Test Information

Test Conditions

Default connections

AVDD, DVDD 5V

Forced Pins INP

Measured Pins OUTP

Forced signal level Sine signal, 2V to 3V, 2048 points, 7cycles, 180-degree phase shifted Instrument used to Force Arbitrary waveform generator

(AWG)

Instrument used to measure Digitizer

Pattern dlb

Datasheet Reference

-

Test Number 14

Test Name DLB_test

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VOL = 2.4V VOH = 2.6V

Sampling frequency: 64kHz(INP) 64kHz(OUTP)

Test Procedures

3. Input sine signal through AWG, trigger one vector before the ramp signal 4. Capture OUTP signal through digitizer

6. Calculate Signal-to-Noise Ratio (SNR), Total Harmonic Distortion (THD) and 2nd and 3rd harmonics.

Figure 3.4.5.9.1 Digital loopback test

Loop back test is the additional test usually tests for certain IC that consists loop back operation. There have two type of loop back which are analog and digital

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digital loop back and then the INP pin is connected with AWG for sending the analog waveform to DUT. Analog waveform converts from analog to digital as output waveform. If digital loopback enable, digital output loop back to become digital input for DAC conversion to become output analog waveform .Then, this waveform is captured by digitizer at OUTP pin and display the results.

3.5 Summary

In this chapter, it will provide the steps on the developing the test program V93K dual sites on TLV320AIC10 and also including additional test which is digital loop back test mode. In this chapter also described how to create the test plan for this device.

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CHAPTER 4

RESULT AND DISCUSSION 4.1 Overview

This chapter presents the result and discussion for the tests that have been carried out.

Generally, this chapter is consisted into several section as in each section the result obtained are analyzed and being discussed. The first part is the analysis on the verification of test flow. Next, the second part is mixed signal testing and some additional test which is digital loop-back test mode. Besides, the analysis of certain tests using oscilloscope besides refer to datasheet to verify the result for comparison.

All the results are used to prove the test program on DUT that shows all tests pass and characterization for the whole concept.

4.2 Verify the Test flow

Figure 4.2.1 Test flow verification

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Figure 4.2.1 shows that the final test flow and the result showed all tests passed in dual sites. The results are displayed in report UI for all tests, timing diagram for functional test and signal analyzer for distortion test for ADC, DAC and digital loopback test. Besides, test flow also showing the execution time for each tests.

Execution time is timefor each test during execution process. It also called as test time.

Figure 4.2.2 Test flow group

Figure 4.2.2 shows test flow for common test and additional test include the test time. The test time result for common test is 518.26ms. For additional test, the test time is 196.462ms. Therefore, the total test time is 714.722ms in dual site. This total value only does not include time of prober place on the DUT on tester.

Based on test time for each test suite, the test time for continuity test is 15.488ms. The test time for leakage test is 18.353ms. Functional test is to verify pattern “Funct1” and “Funct2”. Thus, overall test time for functional test is 37.828ms.

Besides, test time for dynamic current test for AVDD and DVDD test suites is 9.857ms. The test time for reference voltage test (VMID) is 8.614ms. The overall test time for frequency test is 90.724ms. Distortion test for ADC and DAC, the overall test time is 337.213ms.

Figure 4.2.3 Execution time for each test

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4.2.1 Continuity Test

Figure 4.2.1.1 Continuity test suite

Figure 4.2.1.1 shows the test suite for continuity after execution and display green sign that showing this test is passed. Figure 4.2.1.2 shows the result for continuity test.

Figure 4.2.1.2 Continuity test report UI

Based on this result, the measuring voltage for digital pins are approximate - 480mV. All digital pins passed because this value lied on the pass limit -600mV to - 200mV. When a current is forced into VDD pins, the voltage will rise to a range

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between short limit (-600mV) and open limit (-200mV). In this result only focus single polarity which is continuity negatively.

4.2.2 Leakage Test (IIH,IIL)

Figure 4.2.2.1 Leakage test suite

Figure 4.2.2.1 shows the leakage test passed for low and high current leakage after execution and the result is shown in Figure 4.2.2.2.

Figure 4.2.2.2 Leakage test report UI

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Based on this result, all selected pins are passed because the measuring current for Input low leakage current (IIL) and Input high leakage current (IIH) are lied on pass limit -1mA to 1mA. Almost all selected pins, the value for IIL and IIH are 0uA.

It means there is not unwanted current paths on selected pins to VDD at condition input logic ‘0’ and ‘1’. Based on datasheet, the maximum value IIL and IIH are 10uA.

Therefore, the result got from report UI overall are not more than 10uA.

4.2.3 Functional Test

Figure 4.2.3.1 Functional test group

Figure 4.2.3.2 Functional test report UI

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For functional test, pattern that needed to be verified are “Funct1” and

“Funct2”. The result showed these patterns pass on report UI in figure 4.2.3.2. It is because this test only verified the pattern or true table pass or fail. The result is described from timing diagram the MCLK, SCLK and FS waveform. Timing diagram is a tool that allowing to display the waveform sending to DUT and the response from the DUT output. Thus, MCLK is input waveform and SCLK and FS are input and output waveform.

Figure 4.2.3.3 Timing diagram "funct1"

Figure 4.2.3.3 shows the timing diagram for primary serial communication.

Before 5231 cycle, the FS is at low and “don’t care” conditions because of stabilizing the device before FS is triggered at this cycle. SCLK and FS are tracking at 5231 cycle to synchronize the signal between SCLK and FS. Therefore, this waveform follows from datasheet for primary serial communication.

Figure 4.2.3.4 Timing diagram "Funct2"

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Figure 4.2.3.4 shows the timing diagram for secondary serial communication.

Before 5231 cycle, the FS need to assign “don’t care” condition because based on datasheet to perform the secondary serial communication, DIN should be at high (D0=1) at fourth interval FS and also to stabilize device. From this timing diagram, FS started going high at fourth interval FS. This control is software secondary request control. Therefore, this waveform also follows datasheet.

4.2.4 Dynamic Current Test (AVDD/DVDD)

Figure 4.2.4.1 Dynamic current test suite

Based on these test suites, AVDD and DVDD are passed and the result displayed in report UI that shows in figure 4.2.4.2.

Figure 4.2.4.2 Dynamic current test report UI

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Based on Report UI, operating current (IDD) for AVDD when AVDD is 5V in site 1 and site 2 are 17297.793uA and 16688.295uA respectively. Comparing these values from datasheet, the specification value of IDD when AVDD = 5V is 14.8mA. It shows that these values are slightly different with specification value. The simulation values are more than the specification value. The different value between simulation and specification value for site 1 is approximate 2.5mA and site 2 is approximate 1.9mA. But these values consider passed. It is because these values are in a range of test limit from 5000uA to 20000uA.

Besides, operating current (IDD) for DVDD when DVDD is 5V for site 1 and site 2 are 1217.516uA and 1251.198uA respectively. Based on datasheet, the specification value of IDD when DVDD = 5V is 2.3mA. Comparing with simulation values, these values slightly different which specification value with different value approximately 1.2mA. These values still passed because it lied on range of test limit, 100uA to 5000uA.

4.2.5 Reference Voltage Test (VMID)

Figure 4.2.5.1 Reference voltage test suite

Figure 4.2.5.1 shows the test suite for reference voltage test and get passed.

Report UI for VMID is displayed in figure 4.2.5.2.

Figure 4.2.5.2 VMID report UI

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Based on figure 4.2.5.2, Reference voltage (VMID) for site 1 and site 2 are 2.51065V and 2.48653V respectively. Refer from datasheet, the actual VMID value should be around 2.5V. It is because this value can be described from calculation,

𝑉𝑀𝐼𝐷 = 𝐴𝑉𝐷𝐷 2⁄ = 5𝑉 2⁄

= 2.5𝑉

Where AVDD is setup to 5V

Comparing the result with datasheet, VMID values are slightly different with different value between actual and simulation VMID value for site 1 and site 2 are 0.01V and -0.02V respectively. These values are still passed because these lied in the rage of test limit which is 2.45V to2.55V.

4.2.6 Frequency Test (SCLK/FS)

Figure 4.2.6.1 Frequency test suite

Figure 4.2.6.1 shows the frequency test suite passed and report UI is explained in figure 4.2.6.2.