PST ON ESD AND

SAFETY PROCESS ANALYSIS:

PST ON ESD AND

ALARM

SAFETY DESIGN

EVALUATION

By

SYAMSUL FAIZAL B. IDRIS

FINAL PROJECT REPORT

Submitted to the Electrical & Electronics Engineering Programme in Partial Fulfillment of the Requirements

for the Degree

Bachelor of Engineering (Hons) (Electrical & Electronics Engineering)

Universiti Teknologi Petronas Bandar Seri Iskandar 31750 Tronoh

Perak Darul Ridzuan

© Copyright May 2011 by

Syamsul Faizal b. Idris, 2011

CERTIFICATION OF APPROVAL

SAFETY PROCESS ANALYSIS:

PST ON ESD AND

ALARM & SAFETY DESIGN & EVALUATION

Approved:

by

Syamsul Faizal b. Idris

A project dissertation submitted to the Electrical & Electronics Engineering Programme

Universiti Teknologi PETRONAS in partial fulfilment of the requirement for the

Bachelor of Engineering (Hons) (Electrical & Electronics Engineering)

AP. Dr. Nordin b. Saad Project Supervisor

UNIVERSITI TEKNOLOGI PETRONAS TRONOH, PERAK

May2011

CERTIFICATION OF ORIGINALITY

This is to certify that I am responsible for the work submitted in this project, that the original work is my own except as specified in the references and acknowledgements, and that the original work contained herein have not been undertaken or done by unspecified sources or persons.

Syamsul Faizal b. Idris

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ACKNOWLEDGEMENTS

First and foremost, I am very grateful to God the Almighty for His mercy as He gave me the strength and ability to complete the final year project throughout the year. I also would like to take this opportunity to thank all parties involved in making the final year project a great educational session and a success. My deepest gratitude goes to my family.

I would like to thank the following individuals for their respective professionalism and contribution to the program. Special thanks go to:

AP. Dr. Nordin b. Saad FYP Supervisor, UTP Ir. Dr. Idris b. Ismail FYP Co-Supervisor, UTP Mr. Azhar b. Zainal Abidin Senior Technician, UTP

I would like to thank everyone for their continuous support especially my colleagues and fellow friends. These elements have successfully assisted me to do my best and effort in upholding the individual learning spirit during my final year in UTP. Thank you once again to everyone involved.

1ll

ABSTRACT

Looking from the defmition of the word disaster, it is defined as an unexpected natural or man-made catastrophe of substantial extent causing significant physical damage or destruction, loss of life or sometimes permanent change to the natural environment. Putting in a scenario of a very critical process plant where every action and decision must be analyzed into every minute detail, it is where even the slightest mistake would have an effect on the major process.

What more if a disaster should occurred in the plant, the effect would have been unimaginable. In the effort of avoiding such incidence, various countermeasures had been deployed to make sure that every possible case is handled. Among the main and early stage preventive device is the Emergency Shutdown Valve (ESD), place in between the upstream/downstream inventory and the processing plant.

The scope of this project is to develop a reliable and efficient controller configuration for the ESD to perform Partial Stroke Testing (PST) and Full Stroke Testing (FST) as per demand. It is important for the controller to ensure the device to perform as per needed, reducing the risk of accidents and mishaps. In the fast moving pace of current technology, newer hardware improves the efficiency of the testing process, thus providing easier insight into the procedure. The use of the ABB Progranunable Logic Control (PLC) together with its progranuning software CoDeSys provides clearer view of the procedure. The report also details the development of the controller function block such as the Proportional Band, PID and process monitoring that includes Alarm & Safety System. The analysis of an actual plant, namely the PETRONAS Carigali RESAK Plant is also included, together with its case study. The findings further demonstrate the importance of the ESD and the FST/PST procedure gained from effective procedure progranuning and thorough data analysis.

IV

TABLE OF CONTENT

ABSTRACT.

LIST OF FIGURES . LIST OF TABLES .

CHAPTER llNTRODUCTION 1.1 Background of Study 1.2 Problem Statement

1.3 Objectives & Scope of Study CHAPTER 2 LITERATURE REVIEW

2J Prutial Stroke Test (PST) .

2.2 ABB PLC Testing and Simulation CHAPTER 3 METHODOLOGY

3.1 Procedure Identification for PST .

3.2 Procedure identification tor Alarm & Safety System CHAPTER 4 RESULT AND ANALYSIS

4.1 PST Data Safety Analysis.

4.2 PLC Plant Example

4.3

CHAPTER 5 CONCLUSION AND RECOMMENDATIONS 5.1 Conclusion

5.2 Reconnnendations.

REFERENCES

APPENDIX .

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LIST OF FIGURES

Figure 1: Safety Layer of Plant Protection

Figure 2: ROTORK Smart Valve Monitor (SVM) Figure 3: ABB PLC ACSOO Hardware

Figure 4: Example ofPLC connection for AC500 Figure 5: Procedure Identification for PST .

Figure 6: Procedure Identification for Alarm & Safety System Figure 7: Simple Plant Feed Diagram.

Figure 8: Choosing PLC hardware version Figure 9: Navigating to the PLC configuration Figure 10: Hardware module options .

Figure 11: Module parameters checking Figure 12: Ethernet slot definition Figure 13: Input assignment . Figure 14: Output assignment.

Figure 15: Navigating to communication parameters option.

Figure 16: Protocol options for progranuning Figure 17: Address and port determination Figure 18: Device appearance.

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Figure 19: Program simulation overview

Figure 20: GT and REAL_ TO_ INT block diagram Figure 21: AC500 block diagram

Figure 22: PID function block from CoDeSys Figure 23: Process visualization

Figure 24: Voltage source schematic .

Figure 25: Example of potentiometer wiring.

Figure 26: Current source circuit schematic Figure 27: Effect ofDCpc on Tlpc

Figure 28: Effect ofDCpc on Tlpc- Positioner vs. SVM Figure 29: PST/FST Flow Diagram

Figure 30: Variable declarations Figure 31: Alarm Detection block

Figure 32: LD for the PST/FST/Alarrn Sequence Figure 33: Proportional band .

Figure 34: Declaration of Proportional Band Function Block Figure 35: Proportional band with specified variable.

Figure 36: Proportional band LD Switch

Figure 37: Testing Upper Proportional Band (PV = 62%) Figure 38: Testing Lower Proportional Band (PV = 38%)

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