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DESIGN RULE CHECK TO VALIDATE OPTION METAL AND VIA FOR A PREPROGRAMMED

LAYOUT DESIGN

By

SUREINDRA KUMAR A/L OOTHAYER KUMAR

A Dissertation submitted for partial fulfilment of the requirement for the degree of Master of Science

July 2014

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Acknowledgement

Designing the algorithm to check the option metal and via had been the pinnacle of my life in learning and gain enormous knowledge. Through this project I have gained a great skills and experience in designing Design Rule Check algorithms for verification by doing research and simulations.

I also would like to take this opportunity to express my sincere gratitude to my supervisor Dr. Asrulnizam Abd Manaf for his time, support, encouragement and guidance through this project phase. Without his guidance and generosity in imparting his knowledge and experience had become a tremendous approach towards completing each phase of this project.

Besides, I would like to extend my sincere thankfulness to my supervisor in Altera, Mr Eric Leong, who guide me through the completion of the project. He also had been very supportive and encouraging in the process of completing the final phase of the project.

Lastly, I like to thank my family, friends and USM staff who shared their love, encouragement and never ending support throughout all situation of happy and obstacles faced.

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iii

Table of Contents

Acknowledgement………. ii

Table of Content……… iii

List of Tables………. ix

List of Figures and Illustrations……… xi

List of Abbreviations and Nomenclature……….. xiii

Abstrak……….. xiv

Abstract………. xv

CHAPTER 1……….. 16

INTRODUCTION………. 16

1.1 Introduction………. 16

1.2 Problem Statement……….. 17

1.3 Project Objective………. 19

1.4 Project Scope………... 19

1.5 Outline of Project Report……… 19

CHAPTER 2……….. 21

LITERATURE REVIEW……….. 21

2.1 Introduction………. 21

2.2 Brief History……… 22

2.3 Layout Design………. 23

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2.3.1 Layers and Connectivity……… 24

2.4 DRC Overall Idea……… 25

2.4.1 Process Design Rules………. 25

2.4.2 Layout Design Rules……….. 26

2.4.3 DRC General Procedure to Follow……… 28

2.4.4 Dimensional Rule Checks……….. 29

2.4.5 Polygon-Directed Rule Checks……….. 31

2.5 Algorithm used previously for DRC………... 32

2.5.1 Yield improvement technique using local design rules……… 32

2.5.2 Compact layout rules Extraction for latchup prevention………….. 34

2.5.3 Rectangle and Raster Scan Method………... 36

2.5.4 Chip Level Design Rule Evaluator (ChipDRE)………. 37

2.5.5 Design Rules to Optimize the Layout of the Multilayer Circuit Package………... 39 2.5.6 Lyra: Geometry Layout Rule Checking………. 39

2.5.7 Layout Level Design for Testability Rules……… 40

2.5.8 Design Rule for Evaluation (DRE).………... 41

2.5.9 Design Rules Description for Automated Layout Tools………... 41 2.5.10 A O (n log m) algorithm for VLSI Design Rule……….. 43

2.5.11 Parallel Algorithm for Layout Compaction………. 43

2.5.12 Design Rules for CMOS-MEMS Layouts………... 43

2.5.13 Summary of design rules 45 2.6 Option Layers……….. 49

2.6.1 Layout of Circuits Designed for Change………... 49

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2.6.2 Metal Option Programmability……….. 49

2.6.3 Options Implementation in Design Flow………... 51

2.6.4 Via Programmability……….. 53

2.7 Metal and Via Layer……… 55

2.7.1 The Bonding Pad………... 55

2.7.2 Design and Layout Using the Metal Layers……….. 56

2.7.2.1 Metal1 and Via1……… 57

2.7.3 Large Metal Via Implementation………... 58

2.8 20nm Detailed Coverage……… ……… 60

2.8.1 Introduction……… 60

2.8.2 Challenges……….. 61

2.9 Design Automation………. 64

2.9.1 Design Entry……….. 64

2.9.2 Synthesis……… 65

2.9.3 Verification……… 65

2.9.3.1 Timing Analysis……… 66

2.9.3.2 Simulation………. 66

2.9.3.3 Emulation……….. 67

2.9.4 Physical Verification……….. 67

2.10 Summary………... 68

CHAPTER 3……….. 69

METHODOLOGY……… 69

3.1 Overall Project Methodology….………... 69

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vi

3.2 The Layout Design Procedure………. 72

3.3 The Layer Types and Data Flow………. 73

3.4 Developing Algorithm………. 74

3.5 Creating Test Patterns………. 75

3.6 Calibre DRC Process………... 76

3.7 DRC Rule Check Operations……….. 77

3.8 Test Patterns and Command Rule used in the Algorithm………... 79

3.8.1 Layer Operations……… 79

3.8.2 Dimensional Check Layer Operations………... 79

3.9 Reference Dictionary………... 83

3.9.1 Boolean AND Operation………... 83

3.9.2 Angle Operation………. 85

3.9.3 Area Operation………... 87

3.9.4 Connect Operation………. 87

3.9.5 Copy Operation……….. 91

3.9.6 Cut Operation………. 91

3.9.7 Enclosure Operation……….. 93

3.9.8 External Operation………. 95

3.9.8.1 Parameters and Descriptions………. 97

3.9.9 Layer Operation………. 97

3.9.10 Layer Map Operation………... 98

3.10 Designing The Algorithm for Option Layer………. 100

3.10.1 Calibre……….. 100

3.11 Designing the Test Patterns for the Option Layer………. 101

3.11.1 Cadence Virtuoso………... 101

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3.11.2 Calibre RVE………... 102

3.12 PERL Programming……….. 102

3.12.1 Subroutines……….. 103

3.12.2 Loops and Decisions……… 104

3.12.3 Pattern Matching……….. 104

3.12.3.1 Copy and Replace……… 104

3.12.4 Reading and Writing……… 105

3.13 Verify Algorithm with Test Patterns………. 106

3.13.1 Lynx Software……….. 106

3.14 Switching Method used in Option Metal/Via………... 106

3.15 Summary………... 107

CHAPTER 4……….. 108

RESULT AND DISCUSSION……….. 108

4.1 Metal layer description…...………. 108

4.2 Algorithm evaluation process…..……… 110

4.3 Reason Behind Multiple Modes/Types and Additional Rules……… 112

4.4 Test Patterns……… 116

4.5 Automation Process………... 120

4.6 PERL Programming……… 121

4.6.1 View Difference using Tkdiff……… 121

4.7 Rule Description……….. 126

4.8 Importance of Generating Three Modes of Runsets………... 127

4.9 Result For Tested Test Pattern……… 128

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4.10 Result for Metal Rules………... 138

4.11 Result For Via Rules………... 141

4.12 Summary………... 144

CHAPTER 5……….. 145

CONCLUSION………... 145

5.1 Conclusion…..………. 145

5.2 Future Works………... 146

REFERENCES……….. 148

APPENDIX ...………... 151

Appendix 1….…….……….. 151

Appendix 2 ………... 154

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ix List of Tables

Table 2-1 Summary of design rules……… 45

Table 3-1 Examples of DRC Rule Check Operations……… 78

Table 3-2 Layer operations: Dimensional Check Operations………. 80

Table 3-3 Layer Operations: Auxiliary Operations……… 81

Table 3-4 Syntax command example for AND……….. 83

Table 3-5 The parameter description for AND expression……… 84

Table 3-6 Possible choice for electrical nodes of polygons………... 84

Table 3-7 The parameter description for Connect operation……….. 88

Table 3-8 The parameter description for Cut operation………. 91

Table 3-9 The parameter description for Layer Map operation…………. 99

Table 3-10 Types of checks covered for both Metal and Via………... 100

Table 3-11 Layers included in each mode……… 103

Table 3-12 Copy and replace example………. 105

Table 4-1 Metallization option for metal and via………... 109

Table 4-2 Layer covered by each mode……….. 112

Table 4-3 New Rules for worst case checking………... 113

Table 4-4 Worst case test pattern……… 117 Table 4-5 Comparison of changes made before and after automation in

Metall_Viareal mode………..

122 Table 4-6 Comparison of changes made before and after automation

Vial_Metalreal mode………

123 Table 4-7 Comparison of changes made before and after automation

Metal_Viall

124 Table 4-8 Comparison of changes made before and after automation for

new

125

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rule………...

Table 4-9 Example of result rule description………….……… 128

Table 4-10 Result of the tested Test Pattern………. 129

Table 4-11 Result of the metal rules………. 140

Table 4-12 Result of the via rules………. 143

Table A1-1 Result for Metal rules………... 151

Table A2-1 Result for Via rules………... 154

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xi

List of Figures and Illustrations

Figure 2-1 Layout design Procedure……… 29

Figure 2-2a The cross-section view………... 34

Figure 2-2b The equivalent circuit, of the latch up structure in a p-substrate bulk CMOS technology……….. 34 Figure 2-3 A new test method to find layout spacing from I/0 cells to internal circuits and the pickup distances in the internal circuits... 35 Figure 2-4 Example of a twin MOS transistor………. 42

Figure 2-5a Graph showing undercut widths for various inter-structure spaces……….. 44 Figure 2-5b Beam not released due to small spacing………. 44

Figure 2-5c Plate not released because of small etch holes………... 44

Figure 2-5d Released plate………. 44

Figure 2-6 Example of a configurable delay chain……….. 51

Figure 2-7 Delay chain layouts……… 52

Figure 2-8 Decoder architectures………. 55

Figure 2-9 Design rules for the metal layers using CMOSEDU rules………. 56

Figure 2-10 Via1 cell with a rank of 1………... 56

Figure 2-11 Layout and cross-sectional view……… 58

Figure 2-12 An example layout and cross-sectional view using including the n-well……….. 58 Figure 2-13 Cross Sectional view of via cuts………. 59

Figure 2-14 Via array configurations for process reliability……….. 59

Figure 2-15 Via array configurations for circuit performance………... 60

Figure 2-16 Double patterning technology……… 62

Figure 2-17 Double patterning technology decomposition……… 62

Figure 2-18 Decomposition error………... 63

Figure 2-19 Double patterning technology coloring by stitching……….. 63

Figure 2-20 Routing Rules………. 63

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xii

Figure 3-1 Project Flow Chart……….. 71

Figure 3-2 The Layout design procedure………. 72

Figure 3-3 Layer types and data flow in the DRC System……….. 73

Figure 3-4 Development of algorithm……….. 75

Figure 3-5 Creating Test Patterns……… 76

Figure 3-6 Calibre DRC process……….. 77

Figure 3-7 One-layer Boolean AND Operation………... 85

Figure 3-8 Angle Magnitude in Relation to the X-axis……… 86

Figure 3-9 Operation which selects all layer1 edges that conforms to the constraint……… 86 Figure 3-10 Area Operation………... 87

Figure 3-11 Connect………... 89

Figure 3-12a Connect Operation Containing a Contact Layer……… 90

Figure 3-12b Connect Operation Containing a Contact Layer with invalid connection……….. 90 Figure 3-13 Cut……….. 93

Figure 3-14 Basic Enclosure Rule Checks………. 94

Figure 3-15 Typical enclosure check………. 94

Figure 3-16a Basic External Rule Check for single layer……….……... 96

Figure 3-16b Basic External Rule Check for two layer...……….……... 96

Figure 3-17 Typical External check………... 97

Figure 3-18 If-else operation presented in boxes………... 104

Figure 4-1 Test pattern for rule VIA1.S.1.6.1……….. 113

Figure 4-2 Three modes with additional rules algorithm development process……… 115

Figure 4-3 Example of result……… 128

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xiii

List of Abbreviations and Nomenclature

Abbreviation ACA

ALADIN CAD CAE ChipDRE CMOS DRE DA DFM DFT DPT DR DRC DRE EDA ESD FIB FPGA GCPW GDR GDS HP IC ILD I/O LDR LI LLDFT LVS LVTTL NMOS PCB PLD PLL PMOS RDR ROM SLP SoC SSTL SVRF TSMC TTL VLSI

Meaning

Ant Colony Algorithm

Automatic Layout Design Aid for Analogue Integrated Circuit

Computer Aided Design Computer Aided Engineering Chip Level Design Rule Evaluator

Complementary Metal-Oxide Semiconductor Design Rule for Evaluation

Design Automation

Design For Manufacturability Design For Testability

Double Patterning Technology Design Rule

Design Rule Check Design Rule Evaluator

Electronic Design Automation Electrostatic Discharge

Focused Ion Beam

Field Programmable Gate Arrays Good Chip Per Wafer

Global Design Rules Graphic Database System High Performance

Integrated circuit Interlayer Dielectric Input/output

Local Design Rules Local Interconnects

Layout Level Design For Testability Layout versus Schematic

Low Voltage Transistor-transistor Logic Level N-type Metal Oxide Semiconductor Logic Printed Circuit Board

Programmable Logic Devices Phased Lock Loop

P-type Metal Oxide Semiconductor Logic Restrictive Design Rules

Read Only Memory Super Low Power System on Chip

Stub Series Terminated Logic Standard verification Rule Format

Taiwan Semiconductor Manufacturing Company Transistor-transistor Logic

Very Large Scale Integration

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xiv Abstrak

Transistor diskala pada skala kecil untuk meningkatkan bilangan transistor dalam sebuah cip tunggal dan menyumbang kepada variasi blok IP. Justeru itu, rekabentuk susun atur menjadi kompleks dan proses mengesahkan rekabentuk susun atur akan menjadi semakin mencabar. Penggunaan lapisan pilihan telah dikenal pasti di mana ia akan mempunyai satu litar dan susun atur asas. Selepas susun atur selesai direka, ia adalah sangat mudah untuk menukar logam dan lubang hubung pilihan kepada logam dan lubang hubung sebenar. Walau bagaimanapun, pengesahan konvensional menggunakan peraturan rekabentuk (DRC) di CADENCE tidak meliputi pemeriksaan pada lapisan pilihan. Lapisan pilihan pada susun atur yang diprogramkan tidak disahkan betul dan boleh menyebabkan ralat. Projek ini akan membolehkan pengesahan lapisan pilihan dengan membangunkan satu algoritma yang dapat meliputi pemeriksaan untuk kedua-dua lapisan pilihan dan sebenar bagi logam dan lubang hubung. Projek ini adalah berdasarkan pada proses 20nm TSMC dan pengubahsuaian dibuat bagi membolehkan pemeriksaan pada lapisan pilihan.

Pengubahsuaian dibuat dengan cepat dan pemeriksaan kes terburuk dapat dilakukan melaui proses automasi kod dengan mengunakan Pengekstrakan praktikal dan Laporan Bahasa (PERL). Hasilnya ditunjukkan dengan melukis corak ujian dengan peraturan rekabentuk. Contohnya, jika satu peraturan dengan spesifikasi lebih daripada atau sama dengan 0.05nm dilukis pada spesifikasi kurang daripada 0.05nm akan menyebabkan ralat. Pendekatan ini telah digunakan bagi semua peraturan reka bentuk yang terlibat dalam teknologi proses 20nm. Kaedah yang dicadangkan untuk mengesahkan lapisan pilihan berjaya dan kesilapan yang paling kerap berlaku pada peringkat awal merekabentuk susun atur dapat dikurangkan.

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xv Abstract

Transistor sizing had been scaled down to increase the number of transistors in a single chip which also leads to the variation of IP blocks. Consequently, the layout design becomes very complex and it is challenging to verify the layout design.

Therefore, the option layer had been identified where it will have a common base circuitry and layout. After the layout is completed, it is very convenient to convert the option metal and via to real metal and via layer. However, the conventional verification using the design rule check (DRC) in Cadence does not include the check for option layer. Option layer on preprogrammed layout are not verified correct and may cause a violation. Thus, this project will enable the verification of the option layer by developing an algorithm which able to cover the check for both option and real metal/via layer. This project will be based on TSMC 20nm process library and the modifications are made to enable the option layer check. In order to enable the modification to be made quickly and enable worst case check, Practical Extraction and Report Language (PERL) programming used to automate the code.

The result is shown by drawing the test pattern with design rule. As example, a rule with specification of more than or equal with 0.05nm will flag an error if the test pattern is drawn less than 0.05nm. This approach had been applied to all the design rules involved in 20nm process technology. The method proposed validates the option layer successfully and most errors found in the early stage of designing the layout are minimized.

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16 CHAPTER 1

INTRODUCTION

1.1 Introduction

The invention of the integrated circuit (IC) by Jack Kilby in 1958 had contributed to the advancement of technology. Integrated circuit (IC) technology has become the fundamental technology towards the development of the innovative devices and systems. The past decades have seen how these small silicon chips gradually prevail and play an indispensable role in our life. ICs can be found in almost every electronic device designed in the new era.

The process of developing IC manufacturing process had never stop from meeting the increasing demands for new products with higher performance and strong functionality. As the feature size scales down, a single transistor runs faster and consumes less power.

IC designers are able to pack more transistors into a single chip and make the chip more powerful. The trend of increasing number of transistors follows Moore’s law, who predicts that the number of transistors being packed into a single integrated circuit doubles around every 18 months. This law had been carried out till today, where the ICs are designed at 14nm process technology. Besides, this integration

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allowed us to build systems with more transistors by allowing more computing power to be applied to solve a problem.

Integrated circuits are also easier to be designed, manufactured and are more reliable than discrete systems. However, as the size of the transistor shrinks into nanometer scale, it becomes a challenge for IC manufacturer to achieve both good manufacturability and cost efficiency. Apart from that, IC manufacturers also face many challenges in the more sophisticated manufacturing process which includes, increasing circuit complexity, sub-wavelength lithography, and use of new materials for interconnect and dielectric (Antonsson, 2003) (Kai-Ti Hsu, 2012) (Tseng-Chin Luo, 2012) (Wolf, 2008).

1.2 Problem Statement

Most of the fabless companies are involved in the process of designing ICs for various usages. They use various designing tools to automate the design and validate the design process. The custom mask layout is designed based on the rules and parameters provided by foundry. After the designing process is completed, an algorithm is developed to validate the mask layout. The algorithm was developed from the Standard Verification Rule Format (SVRF) and foundry technology. This algorithm helps to verify the mask layout in order to prevent any Design Rule Check (DRC) violation.

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Most of the mask layouts are predesigned with option metal and via to ease the layout designing process. The option layer is converted from option to real from time to time until the final design is completed. However, current preprogrammed mask layout with option layer does not include the Design Rule Check (DRC) for option layer. Therefore, the predesigned location for option metal and via is not verified to be correct and might cause error when converted to real layer.

Consequently, this will cause the preprogrammed mask layout to be redesigned in order to meet the layout designer’s design requirement.

By creating a design rule for the preprogrammed mask layout with the ability to check the optional layer before the real placement could be a solution for this problem. Moreover, this design rule check can be a medium to facilitate the exact position of metal/via without causing any DRC violation. Furthermore, the preprogrammed mask layout can be used as a template for most of the design to cut the cost of production. Since there is no specific rule for the placement of via and metal in the preprogrammed layout at the early stage of design, the validation of the design process is very time consuming and can increase the cost of production.

Besides, the proposed modified algorithm for the option via/metals can contribute towards the validation of the overall design before the placement of via/metal and make the fabrication process much faster.

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19 1.3 Project Objective

The main objective of this project is:

a) To develop an algorithm which is able to check both option metal and option via along with real metal and via.

b) To validate the developed algorithm by testing for the worst case.

c) To develop a Practical Extraction and Report Language (PERL) program to enable the modification to be made to runset level.

1.4 Project Scope

This research is done based on Taiwan Semiconductor Company (TSMC) 20nm process technology. The design rule is referred from TSMC and the algorithm is being modified based from the existing algorithm. The research is being done within Altera organization to improve the design automation process to a new level of validation process.

1.5 Outline of Project Report

The project is organized through five chapters including first chapter.

Chapter 2 focuses on project’s literature review which establishes the academic and research areas related to the project obtained from various sources which includes

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books, journals and articles. This chapter further explains the need for Design Rule Check, the importance of optional layer and previous works related to DRC.

Besides, it also explains some of the commands used in the process of developing the algorithm. Chapter 2 also provides details on previous works related to DRC.

Chapter 2 also serves as a guide and reference for the methodology in Chapter 3.

Chapter 3 is devoted to the project methodology. Methodology includes a discussion of both theoretical issues and practical matters of data collection. The procedures for the overall project methodology and simulation design methodology are expressed with flow charts. Furthermore, this chapter includes brief summary of the information gathered and studied in Chapter 2.

In Chapter 4, a detailed explanation about the finding and analysis of the project, this includes the simulation results and the problems encountered throughout the duration of the project. The results are shown in tables, compared and observed thoroughly.

The Chapter 5 gives an overall conclusion of the project and further recommendation for the project. This chapter summarize the overall work has been done, observed and discovered throughout the project. It also states the project’s objectives have been achieved. Moreover, from the limitations faced by the project, recommendations to further improve the project are given.

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21 CHAPTER 2

LITERATURE REVIEW

2.1 Introduction

Integrated circuit (IC) layout designs have a large number of polygons where it represents different layer of masks. Layout verification determines whether these polygons in a very large scale integration (VLSI) chip comply with all technology requirements. The increasing design complexity and the number of polygons in the different mask layers in a VLSI chip are increasing drastically from time to time.

The processing of the design layout is very time consuming in the layout verification due to the large number of polygons in an IC design. Design Rule Check (DRC) is commonly used to verify a layout design and detects manufacturing rule violations such as width, spacing, and length rules. In reducing the level of process variability, physical-design techniques have been proposed to improve the original IC layout to improve manufacturability (B.W. Lindsay, 1975). The design rule checks (DRC), equation based DRC, layout versus schematic comparison (LVS) and parasitic extraction are provided by the verification tools (Graphics, 2013).

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22 2.2 Brief History

For the past two decades, the electronics industry has grown very drastically both in size and complexity. At early stage of chip design is only to reduce the computer size. However, the reduce size is now being a fundamental measure for computer speed.

Originally, IC layout design was hand-drafted on special paper called Mylar. Due to the market demands and advances in technology brought about an immediate need to develop software and hardware solutions to cater the time-to-market of the chip designs and to automate the entire process. Accuracy of the final masks was also the main concern in the process of computerization of layout design. The very early platforms were custom built to ensure that graphics applications ran quickly and had sufficient capabilities. CALMA (Data General) built main-frame-sized machines and developed specialized software for printed circuit board (PCB) and integrated circuit (IC) applications.

The enormous revolution in hardware was the development of the “engineering workstation,” which ran a version of the UNIX platform. As the hardware platform growth, the software development progressed even faster as indicated by the growing technology. Mentor Graphics, Cadence, Compass and Daisy which gained larger shares of the IC and PCB design tools market.

Towards, upgrading of the software, more automation of the tasks that was labour intensive had been introduced. The significant example of automation includes:

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Layout synthesis: Instead of the conventional methods of manually drawing polygons, layout designs can be created from “code”.

Layout migration: By using mapping and sophisticated compaction techniques layouts can be moved from one set of design rules to another.

Layout verification: Is the tool used to perform design rule checks on the final layout before it sent for production.

Circuit synthesis: Schematics can be automatically generated by using VHDL or Verilog. As more circuitry being produced by this circuit synthesis tools, layout automation such as place-and-route tools had been very essential.

Place-and-route: Optimizing the placement for minimum connectivity, instance placement for literally millions of cells and maximum circuit performance.

The changes make this industry very interesting to be involved. However, the fundamental concepts involved in producing quality layout are based on physical and electrical properties that never change (Clein, 2000).

2.3 Layout Design

Layouts are designed based from transistors, wires and vias. On either side of the gate polysilicon, the P and N bulk regions are defined by diffusing areas. The substrate, contacts and guard rings (other active areas) are formed at the same time.

Contact holes are created in the isolation layer on top of the layer, to enable the interconnect layers to be connected to the polysilicon and/or active areas. The interconnect layers fill the contact holes which was created in the previous step. The final layer is known as the passivation layer with openings for wire bonding

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connections. The passivation layer is a glass layer that separates the chip from the external world (Clein, 2000) (Wolf, 2008).

2.3.1 Layers and connectivity

In most CMOS process, there are four basic layer types. This includes conductors, isolation layers, contacts or vias and implant layers.

1. Conductors: Conducting layers such as diffusion areas, metal and polysilicon layers that are able to carry signal voltages.

2. Isolation layers: Insulator layers which isolate each conductor layer from each other in vertical and horizontal direction to avoid “short circuits” between separate electrical nodes.

3. Contacts or vias: This layer includes metal and via, where it cuts in the insulation layer that separates conducting layers. It also allow the upper layer to contact down through the cut or “contact” hole.

4. Implant layers: These layers customize or modify existing conductor propriety but do not define a new layer or contact.

These four types of layers are used to create transistor devices, resistors, capacitors and interconnections (Clein, 2000).

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