that the

TERIEMAHAN

Please check

that the

examination paper consists

of FOURTEEN printed

pages before you commence this examination.

Answer

all

FOUR questions. Candidates may choose to answer

all

questions in the Malay

Language. If

candidates choose

to

answer

in

the

English

Language,

it is

compulsory

6

answer at least one question in the Malay Language.

UNTVERSITI SAINS

MALAYSIA

Second Semester Examination 2000/2001 Academic Session

February/lvfarc 2001

ZCT t0614 - Electronic

Time :

³

jam

In

Fig.

1.1,

find

the voltage

v

and the current

I

as

indicated.

The diodes drop Vo

:

_0.7V when conducting.

(iii)

2.2K

1.

^(a)

+gv

f'"

If,x I-v v T

_l_ :

-5V

I

'__+ 't*

_l_ :

(D +sv

(iD

1il." T

g :

-9- lzcT

^106l

(4si 100)

(15/100) ...

r0/- (iv)

(b)

10

mA

In

Fig.

1.2, sketch Vo .

(i)

Fig.

1.1

Vp:0.7V.

Fig.

1.2

(ii)

2.2K Ir

^I

V

+72V (c)

2. (a)

For the network of Fig. 2.1

(i)

Determine Zin .

(iD

Calculate the gain.

(iii)

Calculate the cut

off

frequency formed

by Cl.

(iv)

Draw the small signal zc model of the circuit.

Determine

Is , Ic ,

IB and V6p

for the silicon

transistor

circuits

as shown

in

Fig. 1.3. Take _B

=

^100.

(ii)

Fig.

1.3

(40/100)

ttrF

r

V;

^C,

Fig.2.1

F_ vo

Vsp

=

0.7V

D=100

(40/r00)

-t2v

(b)

-

11

-

Find the value of the output vo as indicated

in

Fig. 2.2.

+l2v

2mV

-72V

Fig.2.2

(c)

Determine

Zillandthe

total gain of the

circuit

in Fig. 2.3

Ioss

= lzmA Vp: -6V

Fig.2.3

F=200

Vsp = 0.7V

lzcT 106l

(30/100)

+lgv

4.3K

Vq

-l

z^

r*

I

Fv"

F:

¹⁰⁰

VsB = 0.7V

(30/100)

...12/-

3.

^(a)

(i)

_Calculate the output voltage

for

an

input of V6 =5mV, for

the

circuit

in Fig. 3.1.

Fig. 3.1

Calculate the output voltage

for

the

circuit of fig.

3.2

\lrirthVr :

_40mV

and V2

:20mV.

(ii)

V1

Y2

%

OK

Fig.3.2

(iiD

Determine the output voltage for the

circuit

of Fig. 3.3.

Yz:2Y

Vr=lV

(60/100) 100K

470K

300K

vcr 106l

-13-

Sketch the frequency respollse, indicating the gain

in

dB,

of

the

circuit

shown in Fig. 3.4.

20K

200K

+

4. (a)

Determine

fu

and R" for the transistor switch

if

^l"sut

=

10mA.

o) (i)

vo

50nF

I

F-rt

! rcr'

:

I

\/. _v l_1^I

I

(ii)

Fig. 3.4.

Calculate

the gain of a

negative feedback

amplifier

having loop gain,

A

= -2000 and a feedback factor

I =

^1/10.

F:250 Vs6:0.7V

Fig.4.1.

QOtr00) an open

Q0/t00)

Qotr00)

...

t4/-

10v---:fl_ Vi

+10V

(b)

(i) (ii)

(iii)

Draw a FET phase shift oscillator circuit.

calculate the

operating frequency

of the oscillator if R : 6I(e

_and

C

=

l500pF.

Select a suitable value for Rp

if g, :2mS.

(30/100)

(c)

Calculate the output voltage and the Zener diode current

in

the regulator

circuit

of

Fig.4.2

Vi:

15V

(d)

Fi9.4.2.

Determine the ma:rimum value of load current at

^which

maintained for the

circuit

of Fig. 4.3.

Qo/r00) regulation

is

lI

) )

\

_t

I

\

t ')

V*.=8.5V

vo

0.0lpF

I I

Fig.4.3 9=100

Vee = 0.7V

V^6 = ^7.3V

(30/100)